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    Semiconductor packages having supporting members
    4.
    发明授权
    Semiconductor packages having supporting members 有权

    公开(公告)号：US11676949B2

    公开(公告)日：2023-06-13

    申请号：US17370149

    申请日：2021-07-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taeseok Choi ,  Jihwang Kim ,  Jongbo Shim

    IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

    CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389

    Abstract: A semiconductor package includes a lower substrate including a lower passivation layer, a lower pad, element pads and a supporting pad that are disposed on a lower surface of the lower substrate. The lower passivation layer partially covers the lower pad, the element pads and the supporting pad. A semiconductor chip is disposed on an upper surface of the lower substrate. An upper substrate is disposed on the semiconductor chip and is connected to the lower substrate. An encapsulator is disposed between the lower substrate and the upper substrate. An element is disposed on the lower surface of the lower substrate. The element is bonded to the element pads. A lower supporting member is disposed on the lower surface of the lower substrate. A supporting bonding member bonds the lower supporting member to the supporting pad.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230042622A1

    公开(公告)日：2023-02-09

    申请号：US17742819

    申请日：2022-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim ,  Jinwoo Park

    IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

    Semiconductor package with interposer
    7.
    发明授权
    Semiconductor package with interposer 有权

    公开(公告)号：US11367688B2

    公开(公告)日：2022-06-21

    申请号：US17090502

    申请日：2020-11-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

    Semiconductor device having package on package structure and method of manufacturing the semiconductor device
    8.
    发明授权
    Semiconductor device having package on package structure and method of manufacturing the semiconductor device 有权

    公开(公告)号：US12261157B2

    公开(公告)日：2025-03-25

    申请号：US18372846

    申请日：2023-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeonghyun Lee ,  Jihwang Kim ,  Jongbo Shim

    IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

    Abstract: A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

    SEMICONDUCTOR PACKAGE, AND PACKAGE ON PACKAGE HAVING THE SAME
    10.
    发明申请
    SEMICONDUCTOR PACKAGE, AND PACKAGE ON PACKAGE HAVING THE SAME 有权

    公开(公告)号：US20210257305A1

    公开(公告)日：2021-08-19

    申请号：US17024852

    申请日：2020-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo SHIM ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

    IPC: H01L23/538 ,  H01L25/10

    Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

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