公开(公告)号：US10134486B2

公开(公告)日：2018-11-20

申请号：US15699412

申请日：2017-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonki Kim ,  Yongho Kim ,  Changnam Park ,  Taejoong Song ,  Woojin Rim ,  Jonghoon Jung

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/26 ,  G11C5/02

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.

公开(公告)号：US10049728B2

公开(公告)日：2018-08-14

申请号：US15611274

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonki Kim ,  Jonghoon Jung ,  Yongho Kim

IPC: G11C11/419

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.

公开(公告)号：US09929023B2

公开(公告)日：2018-03-27

申请号：US15350716

申请日：2016-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Jonghoon Jung ,  Sanghoon Baek ,  Seungyoung Lee ,  Taejoong Song ,  Jinyoung Lim

IPC: H01L21/8238 ,  H01L21/3213

CPC classification number: H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.