公开(公告)号：US10050058B2

公开(公告)日：2018-08-14

申请号：US15282206

申请日：2016-09-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

IPC分类号： H01L21/8238 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092 ,  H01L27/11582

摘要： A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20220207393A1

公开(公告)日：2022-06-30

申请号：US17468819

申请日：2021-09-08

申请人： Samsung Electronics Co., Ltd.

发明人： Naoto Umezawa ,  Changwook Jeong ,  Jisu Ryu ,  Kyu Hyun Lee ,  Jinyoung Lim ,  Wonik Jang ,  In Huh

IPC分类号： G06N5/04 ,  G06N5/02

摘要： Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

公开(公告)号：US10541243B2

公开(公告)日：2020-01-21

申请号：US15355159

申请日：2016-11-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jung-Ho Do ,  Seungyoung Lee ,  Jonghoon Jung ,  Jinyoung Lim ,  Giyoung Yang ,  Sanghoon Baek ,  Taejoong Song

IPC分类号： H01L27/11 ,  H01L23/522 ,  H01L23/485

摘要： A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

公开(公告)号：US10037401B2

公开(公告)日：2018-07-31

申请号：US15896415

申请日：2018-02-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Taejoong Song ,  Sanghoon Baek ,  Sungwe Cho ,  Jung-Ho Do ,  Giyoung Yang ,  Jinyoung Lim

IPC分类号： G06F17/50 ,  H01L27/118 ,  H01L27/02

CPC分类号： G06F17/5077 ,  H01L27/0207 ,  H01L27/11807

摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

公开(公告)号：US09929023B2

公开(公告)日：2018-03-27

申请号：US15350716

申请日：2016-11-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jung-Ho Do ,  Jonghoon Jung ,  Sanghoon Baek ,  Seungyoung Lee ,  Taejoong Song ,  Jinyoung Lim

IPC分类号： H01L21/8238 ,  H01L21/3213

CPC分类号： H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

摘要： A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.

公开(公告)号：US09887210B2

公开(公告)日：2018-02-06

申请号：US15238912

申请日：2016-08-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

IPC分类号： H01L21/76 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/8238 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092

CPC分类号： H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

摘要： A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：USRE49780E1

公开(公告)日：2024-01-02

申请号：US16916419

申请日：2020-06-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Taejoong Song ,  Sanghoon Baek ,  Sungwe Cho ,  Jung-Ho Do ,  Giyoung Yang ,  Jinyoung Lim

IPC分类号： H01L27/02 ,  H01L27/118 ,  G06F30/394

CPC分类号： G06F30/394 ,  H01L27/0207 ,  H01L27/11807

摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

公开(公告)号：US10217647B2

公开(公告)日：2019-02-26

申请号：US16032127

申请日：2018-07-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jung-Ho Do ,  Jonghoon Jung ,  Sanghoon Baek ,  Seungyoung Lee ,  Taejoong Song ,  Jinyoung Lim

IPC分类号： H01L21/8238 ,  H01L21/3213

摘要： A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.

公开(公告)号：US09646960B2

公开(公告)日：2017-05-09

申请号：US15046200

申请日：2016-02-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sanghoon Baek ,  Jung-Ho Do ,  Taejoong Song ,  Giyoung Yang ,  Seungyoung Lee ,  Jinyoung Lim

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L27/11 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L27/0207 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104

摘要： A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.