公开(公告)号：US20240363532A1

公开(公告)日：2024-10-31

申请号：US18626985

申请日：2024-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoung Lee ,  Jungho Do

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit includes a standard cell including a first transistor and a second transistor each disposed on a front side of a substrate, a backside via passing through the substrate in a vertical direction with respect to the substrate, a backside wiring layer including a backside power rail disposed on a backside of the substrate and connected with a first source/drain of the first transistor through the backside via, and a backside contact extending in a first direction between the standard cell and the backside wiring layer and electrically connecting a second source/drain of the first transistor with a first source/drain of the second transistor, wherein a bottom level of the backside contact differs from a top level of the backside power rail, and the backside contact is electrically insulated from the backside power rail.

公开(公告)号：US20240303410A1

公开(公告)日：2024-09-12

申请号：US18670009

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  G06F117/12 ,  H01L23/528 ,  H01L29/423

CPC classification number: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/42376 ,  G06F2117/12

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US10541243B2

公开(公告)日：2020-01-21

申请号：US15355159

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Seungyoung Lee ,  Jonghoon Jung ,  Jinyoung Lim ,  Giyoung Yang ,  Sanghoon Baek ,  Taejoong Song

IPC: H01L27/11 ,  H01L23/522 ,  H01L23/485

Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

公开(公告)号：US20230352407A1

公开(公告)日：2023-11-02

申请号：US17853867

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saehan Park ,  Seungyoung Lee ,  Kang-ill Seo

IPC: H01L23/498 ,  H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/49822 ,  H01L23/535

Abstract: Provided is a system for routing connections to a logic circuit, the system including a first wafer having a backside and a frontside opposite the backside, a power conductor at the backside of the first wafer, a core at the frontside of the first wafer, a power via electrically connected to the power conductor and to the core, a signal pad at the backside of the first wafer, a first frontside signal-routing metal at the frontside of the first wafer, and a signal via connected to the signal pad and the first frontside signal-routing metal.

公开(公告)号：US20230326858A1

公开(公告)日：2023-10-12

申请号：US17887203

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Buhyun HAM ,  Byounghak Hong ,  Myunghoon Jung ,  Wonhyuk Hong ,  Seungyoung Lee ,  Kang-ill Seo

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/5329 ,  H01L21/76897

Abstract: Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.

公开(公告)号：US20230307364A1

公开(公告)日：2023-09-28

申请号：US17739717

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/78

CPC classification number: H01L23/5286 ,  H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/7806

Abstract: A semiconductor device including a wafer, a first semiconductor device and a second semiconductor device on a front side of the wafer, power rails on a back side of the wafer, a backside power distribution network (PDN) grid on the back side of the wafer, and front-side signal routing lines above the first and second semiconductor devices on the front side of the wafer. The second semiconductor device is stacked on the first semiconductor device, the backside PDN grid is coupled to the power rails, and the power rails are coupled to the first and second semiconductor devices.

公开(公告)号：US20210334449A1

公开(公告)日：2021-10-28

申请号：US17225773

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/398 ,  H01L23/528 ,  H01L29/423 ,  G06F30/392 ,  G06F30/3953

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US20200220548A1

公开(公告)日：2020-07-09

申请号：US16820835

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Jungho Do ,  Seungyoung Lee ,  Jonghoon Jung

IPC: H03K19/17724 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

公开(公告)号：US12183738B2

公开(公告)日：2024-12-31

申请号：US17221355

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghyun Song ,  Seungyoung Lee ,  Saehan Park

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/423 ,  H10B10/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

公开(公告)号：US12144163B2

公开(公告)日：2024-11-12

申请号：US17382060

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.