-
公开(公告)号：US20230275021A1
公开(公告)日：2023-08-31
申请号：US17738393
申请日：2022-05-06
发明人： BYOUNGHAK HONG , Jeonghyuk Yim , Inchan Hwang , Gilhwan Son , Seungyoung Lee , Saehan Park , Janggeun Lee , Myunghoon Jung , Seungchan Yun , Buhyun Ham , Kang-ILL Seo
IPC分类号： H01L23/528 , H01L23/522 , H01L21/302 , H01L21/8234
CPC分类号： H01L23/5286 , H01L23/5283 , H01L23/5226 , H01L21/302 , H01L21/823475
摘要： Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.
-
公开(公告)号：US10579131B2
公开(公告)日：2020-03-03
申请号：US15814790
申请日：2017-11-16
发明人： Jaecheol Kim , Jinkyu Kim , Dongwoo Kim , Jeongho Kim , Jaesoo Chaung , Jongshik Ha , Heetae Oh , Hyeokseon Yu , Seungyoung Lee , Wooyoung Choi , Jaewoong Han , Mangun Hur
IPC分类号： G06F1/26 , G06F1/32 , G06F1/3296 , G06F1/3206 , G06F15/78 , H03F3/217
摘要： An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.
-
公开(公告)号：US09773772B2
公开(公告)日：2017-09-26
申请号：US15094586
申请日：2016-04-08
发明人： Seungyoung Lee , Sanghoon Baek , Jung-Ho Do
IPC分类号： H01L23/52 , H01L21/4763 , H01L27/02 , H01L23/522 , H01L23/528 , H01L29/78 , H01L29/66
CPC分类号： H01L23/5226 , H01L23/528 , H01L27/0207 , H01L29/66628 , H01L29/7848
摘要： A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.
-
4.发明公开公开(公告)号：US20240363532A1
公开(公告)日：2024-10-31
申请号：US18626985
申请日：2024-04-04
发明人： Seungyoung Lee , Jungho Do
IPC分类号： H01L23/528 , H01L23/522 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/5283 , H01L23/5226 , H01L27/092 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： An integrated circuit includes a standard cell including a first transistor and a second transistor each disposed on a front side of a substrate, a backside via passing through the substrate in a vertical direction with respect to the substrate, a backside wiring layer including a backside power rail disposed on a backside of the substrate and connected with a first source/drain of the first transistor through the backside via, and a backside contact extending in a first direction between the standard cell and the backside wiring layer and electrically connecting a second source/drain of the first transistor with a first source/drain of the second transistor, wherein a bottom level of the backside contact differs from a top level of the backside power rail, and the backside contact is electrically insulated from the backside power rail.
-
5.发明公开公开(公告)号：US20240303410A1
公开(公告)日：2024-09-12
申请号：US18670009
申请日：2024-05-21
发明人： Jisu Yu , Jaeho Park , Sanghoon Baek , Hyeongyu You , Seungyoung Lee , Seungman Lim
IPC分类号： G06F30/392 , G06F30/3953 , G06F30/398 , G06F117/12 , H01L23/528 , H01L29/423
CPC分类号： G06F30/392 , G06F30/3953 , G06F30/398 , H01L23/5283 , H01L23/5286 , H01L29/42376 , G06F2117/12
摘要： A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.
-
公开(公告)号：US10541243B2
公开(公告)日：2020-01-21
申请号：US15355159
申请日：2016-11-18
发明人： Jung-Ho Do , Seungyoung Lee , Jonghoon Jung , Jinyoung Lim , Giyoung Yang , Sanghoon Baek , Taejoong Song
IPC分类号： H01L27/11 , H01L23/522 , H01L23/485
摘要： A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
-
公开(公告)号：US20230352407A1
公开(公告)日：2023-11-02
申请号：US17853867
申请日：2022-06-29
发明人： Saehan Park , Seungyoung Lee , Kang-ill Seo
IPC分类号： H01L23/498 , H01L23/528 , H01L23/535 , H01L21/8238 , H01L21/768
CPC分类号： H01L23/5286 , H01L21/76898 , H01L21/823871 , H01L23/49822 , H01L23/535
摘要： Provided is a system for routing connections to a logic circuit, the system including a first wafer having a backside and a frontside opposite the backside, a power conductor at the backside of the first wafer, a core at the frontside of the first wafer, a power via electrically connected to the power conductor and to the core, a signal pad at the backside of the first wafer, a first frontside signal-routing metal at the frontside of the first wafer, and a signal via connected to the signal pad and the first frontside signal-routing metal.
-
公开(公告)号：US20230326858A1
公开(公告)日：2023-10-12
申请号：US17887203
申请日：2022-08-12
发明人： Buhyun HAM , Byounghak Hong , Myunghoon Jung , Wonhyuk Hong , Seungyoung Lee , Kang-ill Seo
IPC分类号： H01L23/535 , H01L23/528 , H01L23/532 , H01L21/768
CPC分类号： H01L23/535 , H01L23/5286 , H01L23/53209 , H01L23/53257 , H01L23/5329 , H01L21/76897
摘要： Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.
-
9.发明公开公开(公告)号：US20230307364A1
公开(公告)日：2023-09-28
申请号：US17739717
申请日：2022-05-09
发明人： Saehan Park , Seungyoung Lee , Inchan Hwang
IPC分类号： H01L23/528 , H01L27/092 , H01L21/822 , H01L21/8238 , H01L21/78
CPC分类号： H01L23/5286 , H01L27/0922 , H01L21/8221 , H01L21/823871 , H01L21/7806
摘要： A semiconductor device including a wafer, a first semiconductor device and a second semiconductor device on a front side of the wafer, power rails on a back side of the wafer, a backside power distribution network (PDN) grid on the back side of the wafer, and front-side signal routing lines above the first and second semiconductor devices on the front side of the wafer. The second semiconductor device is stacked on the first semiconductor device, the backside PDN grid is coupled to the power rails, and the power rails are coupled to the first and second semiconductor devices.
-
10.发明申请公开(公告)号：US20210334449A1
公开(公告)日：2021-10-28
申请号：US17225773
申请日：2021-04-08
发明人： Jisu Yu , Jaeho Park , Sanghoon Baek , Hyeongyu You , Seungyoung Lee , Seungman Lim
IPC分类号： G06F30/398 , H01L23/528 , H01L29/423 , G06F30/392 , G06F30/3953
摘要： A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.
-
-
-
-
-
-
-
-
-
搜索结果
30 条记录 (耗时 0.019 秒)
