公开(公告)号：US10580733B2

公开(公告)日：2020-03-03

申请号：US15909212

申请日：2018-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hyung Kim ,  Jung-ho Do ,  Dae-young Moon ,  Sang-yeop Baeck ,  Jae-hyun Lim ,  Jae-seung Choi ,  Sang-shin Han

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/118 ,  H01L23/522 ,  H01L27/092 ,  H01L27/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

公开(公告)号：US10515943B2

公开(公告)日：2019-12-24

申请号：US15674931

申请日：2017-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young Lee ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C11/419 ,  G11C5/14 ,  G11C7/18

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

公开(公告)号：US20190355750A1

公开(公告)日：2019-11-21

申请号：US16409129

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho Do ,  Ji-Su Yu ,  Hyeon-gyu You ,  Seung-Young Lee ,  Jae-Boong Lee ,  Jong-Hoon Jung

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

公开(公告)号：US10242984B2

公开(公告)日：2019-03-26

申请号：US15614911

申请日：2017-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Sutae Kim ,  Donghyun Kim ,  Ha-Young Kim ,  Jung-ho Do ,  Sunyoung Park ,  Sanghoon Baek ,  Jaewan Choi

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.