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    Semiconductor devices
    2.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11183497B2

    公开(公告)日：2021-11-23

    申请号：US16531327

    申请日：2019-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Boong Lee ,  Jae-Ho Park ,  Sang-Hoon Baek ,  Ji-Su Yu ,  Seung-Young Lee ,  Jong-Hoon Jung

    IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02

    Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

    INTEGRATED CIRCUITS INCLUDING STANDARD CELLS AND METHODS OF MANUFACTURING THE INTEGRATED CIRCUITS
    4.
    发明申请
    INTEGRATED CIRCUITS INCLUDING STANDARD CELLS AND METHODS OF MANUFACTURING THE INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200050728A1

    公开(公告)日：2020-02-13

    申请号：US16378751

    申请日：2019-04-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JIN-TAE KIM ,  Sung-We Cho ,  Tae-Joong Song ,  Seung-Young Lee ,  Jin-Young Lim

    IPC: G06F17/50 ,  H01L27/02

    Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.

    System on chip
    6.
    发明授权
    System on chip 有权
    片上系统

    公开(公告)号：US09589955B2

    公开(公告)日：2017-03-07

    申请号：US14872774

    申请日：2015-10-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11

    CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    Abstract translation: 提供芯片系统。 片上系统（SoC）包括第一栅极线，第二栅极线和沿第一方向延伸的第三栅极线，栅极隔离区域切割第一栅极线，第二栅极线和第三栅极线并且在 在第一方向上的第二方向，形成在第二栅极线上的第一栅极接触，布置在第一栅极线和第三栅极线之间，并且电连接切割的第二栅极线，形成在第一栅极线上的第二栅极接触， 形成在第三栅极线上的第三栅极触点，电连接第二栅极触点和第三栅极触点的第一金属线以及电连接到第一栅极触点的第二金属线。

    Integrated circuit including clubfoot structure conductive patterns
    7.
    发明授权
    Integrated circuit including clubfoot structure conductive patterns 有权

    公开(公告)号：US11152392B2

    公开(公告)日：2021-10-19

    申请号：US17034602

    申请日：2020-09-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-ho Do ,  Ji-Su Yu ,  Hyeon-gyu You ,  Seung-Young Lee ,  Jae-boong Lee ,  Jong-hoon Jung

    IPC: H01L23/52 ,  H01L27/118 ,  H01L27/02

    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

    System on chip
    9.
    发明授权
    System on chip 有权

    公开(公告)号：US10541237B2

    公开(公告)日：2020-01-21

    申请号：US16037581

    申请日：2018-07-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234 ,  H01L23/528

    Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

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