公开(公告)号：US11289469B2

公开(公告)日：2022-03-29

申请号：US17038292

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Young Lee ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/419 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C5/14 ,  G11C7/18

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

公开(公告)号：US10804257B2

公开(公告)日：2020-10-13

申请号：US16685471

申请日：2019-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young Lee ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/419 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C5/14 ,  G11C7/18

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

公开(公告)号：US10515943B2

公开(公告)日：2019-12-24

申请号：US15674931

申请日：2017-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young Lee ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C11/419 ,  G11C5/14 ,  G11C7/18

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

公开(公告)号：US10922472B2

公开(公告)日：2021-02-16

申请号：US16458225

申请日：2019-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-ho Kang ,  Jae-myoung Lee

IPC: G06F30/398 ,  G03F1/36 ,  H01L21/8238

Abstract: A method of manufacturing a semiconductor device is provided as follows. A mask layout for forming a target pattern of a multi-height cell including a rectangular notch is generated. A preliminary rectangular mask pattern corresponding to the rectangular notch is detected from the mask layout. The multi-height cell is formed of standard cells arranged and connected to each other in a direction and the rectangular notch is disposed between two adjacent standard cells. A hexagonal mask pattern is, in response to the detecting of the preliminary rectangular mask pattern, placed on at least one short side of the preliminary rectangular mask pattern to generate a combined mask pattern. An outer boundary of the combined mask pattern remains in the mask layout and corresponds to the rectangular notch of the target pattern. A target mask and the semiconductor device are formed based on the combined mask pattern.

公开(公告)号：US20200083210A1

公开(公告)日：2020-03-12

申请号：US16685471

申请日：2019-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young LEE ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C11/419

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.