公开(公告)号：US20250031456A1

公开(公告)日：2025-01-23

申请号：US18537211

申请日：2023-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintae KIM ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092

Abstract: Provided is a semiconductor device based on a cell architecture which includes: a 1st semiconductor cell; and a 2nd semiconductor cell which is connected to the 1st semiconductor cell in a 1st direction such that an output pin of the 1st semiconductor cell is connected to an input pin of the 2nd semiconductor cell, wherein the 2nd semiconductor cell is in a form in which the 1st semiconductor cell is turned upside down.

公开(公告)号：US20240313000A1

公开(公告)日：2024-09-19

申请号：US18226328

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintae KIM ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: Provided is a semiconductor device including a 1st frontside metal line at a front side of the semiconductor device; and a 1st backside metal line at a back side of the semiconductor device, wherein the 1st backside metal line is connected to the 1st frontside metal line.

公开(公告)号：US20230343697A1

公开(公告)日：2023-10-26

申请号：US17841245

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggeun LEE ,  Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877

Abstract: A connection structure for an integrated circuit includes: a 1st layer including a 1st metal line; a 2nd layer, above the 1st layer, including a 1st via; and a 3rd layer, above the 2nd layer, including a 2nd metal line connected to the 1st metal line through the 1st via, wherein the 1st via comprises a spacer structure at a side of an upper portion of the 1st via, the spacer structure comprising an insulation material.

公开(公告)号：US20230275084A1

公开(公告)日：2023-08-31

申请号：US17738743

申请日：2022-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Sooyoung PARK ,  Kang-ill SEO

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/822 ,  H01L23/50

CPC classification number: H01L27/0629 ,  H01L27/0688 ,  H01L21/823475 ,  H01L21/8221 ,  H01L23/50

Abstract: Provided is a semiconductor device that includes: at least one field-effect transistor and at least one PN junction device at a lateral side of the at least one field-effect transistor in a 1st layer; and at least one back side power delivery network (BSPDN) structure in a 2nd layer below the 1st layer, wherein the at least one BSPDN structure is configured to connect the at least one field-effect transistor to a voltage source.

公开(公告)号：US20230253327A1

公开(公告)日：2023-08-10

申请号：US17735768

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggeun LEE ,  Kang-ill SEO

IPC: H01L23/535 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895

Abstract: A connection structure of an integrated circuit may include: a top via in a 1st layer; and a super via on the top via, the super via being connected to the top via, wherein the super via penetrates through a 2nd layer, on the 1st layer, and a 3rd layer on the 2nd layer, and each of the 2nd layer and the 3rd layer is provided for formation of at least one metal pattern or at least one via therein.

公开(公告)号：US20230101171A1

公开(公告)日：2023-03-30

申请号：US17536939

申请日：2021-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seungchan YUN ,  Kang-ill SEO

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

公开(公告)号：US20220336582A1

公开(公告)日：2022-10-20

申请号：US17402214

申请日：2021-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho JO ,  Ki-il KIM ,  Byounghak HONG ,  Kang-ill SEO

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.