公开(公告)号：US20250159979A1

公开(公告)日：2025-05-15

申请号：US18606001

申请日：2024-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae PARK ,  Jintae KIM ,  Hyojong SHIN

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Provided is a semiconductor device which includes: a 1st channel structure; a 1st source/drain region and a 2nd source/drain region connected through the 1st channel structure in a 1st direction; a 1st gate structure on the 1st channel structure; a 1st contact structure on the 1st source/drain region and connecting the 1st source/drain region to a voltage source; and a 2nd contact structure on the 2nd source/drain region and connecting the 2nd source/drain region to another circuit element other than a voltage source, wherein a 1st contact area between the 1st contact structure and the 1st source/drain region is greater than a 2nd contact area between the 2nd contact structure and the 2nd source/drain region.

公开(公告)号：US20240290690A1

公开(公告)日：2024-08-29

申请号：US18220432

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae PARK ,  Kang-ill SEO

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device in which a large-CPP area includes a 1st source/drain structure; a 1st frontside contact structure, at a front side of the semiconductor device, connected to the 1st source/drain structure; a 1st via structure, at a lateral side of the 1st source/drain structure, connected to the 1st frontside contact structure; a 2nd via structure on the 1st frontside via structure; a 1st frontside metal line, at the front side of the semiconductor device, connected to the 2nd via structure; and a 1st backside metal line, at a back side of the semiconductor device, connected to the 1st via structure.

公开(公告)号：US20210193657A1

公开(公告)日：2021-06-24

申请号：US16910385

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung KIM ,  Panjae PARK ,  Jaeseok YANG

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

公开(公告)号：US20250167110A1

公开(公告)日：2025-05-22

申请号：US18617033

申请日：2024-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintae KIM ,  Hyo Jong SHIN ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device based on a cell block which may include: a 1st cell comprising a 1st lower active region and a 1st upper active region above the 1st lower active region in a 3rd direction, both being extended in a 1st direction; a 2nd cell comprising a 2nd lower active region and a 2nd upper active region above the 2nd lower active region in the 3rd direction, both being extended in the 1st direction; and a cell spacer between the 1st cell and the 2nd cell in a 2nd direction, wherein no active region is formed in the cell spacer.

公开(公告)号：US20230343825A1

公开(公告)日：2023-10-26

申请号：US17988485

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan PARK ,  Panjae PARK ,  Seungyoung LEE ,  Byounghak HONG ,  Gunho JO

IPC: H01L29/06 ,  H01L27/06 ,  H01L23/48 ,  H01L29/08 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0688 ,  H01L23/481 ,  H01L29/0847 ,  H01L29/78696 ,  H01L27/0886

Abstract: Provided is a three-dimensional stacked (3D-stacked) semiconductor device which includes: a lower active region divided into a lower-1st active sub-region and a lower-2nd active sub-region by at least one lower boundary gate structure; and an upper active region, above the lower active region, divided into an upper-1st active sub-region and an upper-2nd active sub-region by at least one upper boundary gate structure, wherein at least one of the lower boundary gate structure and the upper boundary gate structure is reverse-biased to electrically isolate the lower-1st active sub-region from the lower-2nd active sub-region, and/or electrically isolate the upper-1st active sub-region from the upper-2nd active sub-region

公开(公告)号：US20250031456A1

公开(公告)日：2025-01-23

申请号：US18537211

申请日：2023-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintae KIM ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092

Abstract: Provided is a semiconductor device based on a cell architecture which includes: a 1st semiconductor cell; and a 2nd semiconductor cell which is connected to the 1st semiconductor cell in a 1st direction such that an output pin of the 1st semiconductor cell is connected to an input pin of the 2nd semiconductor cell, wherein the 2nd semiconductor cell is in a form in which the 1st semiconductor cell is turned upside down.

公开(公告)号：US20240313000A1

公开(公告)日：2024-09-19

申请号：US18226328

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintae KIM ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: Provided is a semiconductor device including a 1st frontside metal line at a front side of the semiconductor device; and a 1st backside metal line at a back side of the semiconductor device, wherein the 1st backside metal line is connected to the 1st frontside metal line.

公开(公告)号：US20220328479A1

公开(公告)日：2022-10-13

申请号：US17840060

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung KIM ,  Panjae PARK ,  Jaeseok YANG

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.

公开(公告)号：US20240304520A1

公开(公告)日：2024-09-12

申请号：US18226338

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jintae KIM ,  Panjae PARK

IPC: H01L23/48

CPC classification number: H01L23/481

Abstract: Provided is a semiconductor cell architecture which includes a plurality of cells, a plurality of backside power rails, and a plurality of metal lines, wherein the backside power rails are extended in a cell-length direction, and at least one backside power rail vertically overlaps an inside area of at least one cell without vertically overlapping a lower boundary or an upper boundary of the at least one cell in a plan view.

公开(公告)号：US20240290853A1

公开(公告)日：2024-08-29

申请号：US18373058

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Panjae PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41766 ,  H01L29/401

Abstract: Provided is a semiconductor device which includes: a backside contact plug, formed at a back side of the semiconductor device, below a source/drain region connected to the backside contact plug, wherein the backside contact plug includes a 1st portion which is not vertically overlapped by the circuit element.