公开(公告)号：US11876038B2

公开(公告)日：2024-01-16

申请号：US17469387

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/06 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/06182

Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.

公开(公告)号：US11798883B2

公开(公告)日：2023-10-24

申请号：US17527230

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn ,  Yun Ki Choi

IPC: H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L23/522 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5283 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544

Abstract: A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.

公开(公告)号：US11114524B2

公开(公告)日：2021-09-07

申请号：US16439947

申请日：2019-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jinho Park ,  Yongseung Bang ,  Jeong Hoon Ahn

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L23/532

Abstract: A semiconductor device including a first electrode on a substrate, a second electrode on the first electrode, a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode, a second dielectric layer between the second electrode and the third electrode, and a first contact plug penetrating the third electrode and contacting the first electrode, the first contact plug contacts a top surface of the third electrode and a side surface of the third electrode.

公开(公告)号：US10892318B2

公开(公告)日：2021-01-12

申请号：US16379016

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaofeng Ding ,  Jeong Hoon Ahn

IPC: H01L23/522 ,  H01L29/49 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768

Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.

公开(公告)号：US20200235087A1

公开(公告)日：2020-07-23

申请号：US16569481

申请日：2019-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding

IPC: H01L27/01 ,  H01L23/64 ,  H01L23/522 ,  H01L49/02

Abstract: According to an example embodiment of the present inventive concept, a semiconductor device includes a substrate. A first insulating layer is disposed on the substrate. A thin-film resistor is disposed in the first insulating layer. A capacitor structure is disposed on the first insulating layer and includes a first electrode pattern, a first dielectric pattern, a second electrode pattern, a second dielectric pattern and a third electrode pattern sequentially stacked. A first via is connected to the first electrode pattern and the third electrode pattern. A part of the first via is disposed in the first insulating layer. A second via is connected to the second electrode pattern, and a third via is connected to the thin-film resistor.

公开(公告)号：US10535575B2

公开(公告)日：2020-01-14

申请号：US15997131

申请日：2018-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding ,  Kyoung-woo Lee ,  In-hwan Kim ,  Jong-woon Lee

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/498 ,  H01L25/065

Abstract: An interposer includes a substrate having a mounting area and a test area, first conductive plugs separate from each other, the first conductive plugs being disposed along a first direction and into the test area of the substrate, a first line pattern group including first non-conductive patterns disposed on first centers of the first conductive plugs, and first conductive patterns disposed to bridge first peripheries of a first adjacent pair of the first conductive plugs, and first pads connected to the first conductive patterns at both first ends of the first line pattern group.