公开(公告)号：US10366049B2

公开(公告)日：2019-07-30

申请号：US14568400

申请日：2014-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-seok Kwon ,  Suk-jin Kim ,  Do-hyung Kim

IPC: G06F9/30 ,  G06F15/76 ,  G06F15/78 ,  G06F9/38 ,  G06F15/167

Abstract: A method of controlling a processor includes receiving from a command buffer a first command corresponding to a first instruction that is processed by a second processing core and starting processing of the first command by the first processing core, storing in the command buffer a second command corresponding to a second instruction that is processed by the second processing core before the processing of the first command is completed, and starting processing of a third instruction by the second processing core before the processing of the first command is completed.

公开(公告)号：US20190114542A1

公开(公告)日：2019-04-18

申请号：US16031565

申请日：2018-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava Prasad Nagaraja ,  Dae-hyun Kim ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06N3/08 ,  G06N3/063

Abstract: An electronic apparatus and method thereof are provided for performing deep learning. The electronic apparatus includes a storage configured to store target data and kernel data; and a processor including a plurality of processing elements that are arranged in a matrix shape. The processor is configured to input, to each of the plurality of processing elements, a first non-zero element from among a plurality of first elements included in the target data, and sequentially input, to each of a plurality of first processing elements included in a first row from among the plurality of processing elements, a second non-zero element from among the plurality of elements included in the kernel data. Each of the plurality of first processing elements is configured to perform an operation between the input first non-zero element and the input second non-zero element, based on depth information of the first non-zero element and depth information of the second non-zero element.

公开(公告)号：US10185565B2

公开(公告)日：2019-01-22

申请号：US15100452

申请日：2014-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-un Park ,  Tai-song Jin ,  Do-hyung Kim ,  Suk-jin Kim

IPC: G06F9/30 ,  G06F15/78

Abstract: Provided are a method and an apparatus for controlling a register of a reconfigurable processor. The power of a register may be efficiently used by obtaining a command for each of a plurality of read ports of the register from a memory, obtaining activation information for each of the plurality of read ports from the obtained command, and determining an address value of each of the plurality of read ports on the basis of the obtained activation information.

公开(公告)号：US09804853B2

公开(公告)日：2017-10-31

申请号：US14258640

申请日：2014-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Un Park ,  Suk-jin Kim

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30178

Abstract: Provided are an instruction compression apparatus and method for a very long instruction word (VLIW) processor, and an instruction fetching apparatus and method. The instruction compression apparatus includes: an indicator generator configured to generate an indicator code that indicates an issue width of an instruction bundle to be executed in the VLIW processor, and a number of No-Operation (NOP) instruction bundles following the instruction bundle; an instruction compressor configured to compress the instruction bundle by removing at least one of NOP instructions from the instruction bundle and the NOP instruction bundles following the instruction bundle; and an instruction converter configured to include the generated indicator code in the compressed instruction bundle.

公开(公告)号：US20150154026A1

公开(公告)日：2015-06-04

申请号：US14554785

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-un PARK ,  Suk-jin Kim ,  Do-hyung Kim

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3016 ,  G06F9/3822 ,  G06F9/3853

Abstract: In a method to execute instructions, at least one instruction executed in a predetermined cycle is acquired based on information included in each of a plurality of instructions, and a code included in the at least one instruction acquired. An instruction is allocated to at least one slot based on the analysis result, and a slot necessary to execute the instruction is selectively used. Accordingly, power consumption of a device using the method may be reduced.

Abstract translation: 在执行指令的方法中，基于包括在多个指令中的每一个中的信息以及包含在所述至少一个指令中的代码，获取在预定周期中执行的至少一个指令。 基于分析结果将指令分配给至少一个时隙，并且选择性地使用执行指令所需的时隙。 因此，可以减少使用该方法的装置的功耗。