公开(公告)号：US11568303B2

公开(公告)日：2023-01-31

申请号：US16153135

申请日：2018-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-soo Lee ,  Dae-hyun Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06N20/00

Abstract: An electronic apparatus is provided. The electronic apparatus includes a first memory configured to store a first artificial intelligence (AI) model including a plurality of first elements and a processor configured to include a second memory. The second memory is configured to store a second AI model including a plurality of second elements. The processor is configured to acquire output data from input data based on the second AI model. The first AI model is trained through an AI algorithm. Each of the plurality of second elements includes at least one higher bit of a plurality of bits included in a respective one of the plurality of first elements.

公开(公告)号：US10586797B2

公开(公告)日：2020-03-10

申请号：US15486681

申请日：2017-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon Kim ,  Hong-soo Kim

IPC: H01L27/115 ,  H01L27/105 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/28 ,  H01L23/528 ,  H01L29/78 ,  G11C16/04 ,  H01L27/11565

Abstract: A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.

公开(公告)号：US11093439B2

公开(公告)日：2021-08-17

申请号：US16143922

申请日：2018-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava prasad Nagaraja ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06F9/30 ,  G06N3/08 ,  G06F15/80 ,  G06F7/544 ,  G06N20/00 ,  G06N3/04 ,  G06N3/063

Abstract: A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.

公开(公告)号：US10283451B2

公开(公告)日：2019-05-07

申请号：US15810289

申请日：2017-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-hoon Kim ,  Woo-sung Yang ,  Jee-hoon Hwang

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/321 ,  H01L27/11582 ,  H01L21/3213 ,  H01L49/02 ,  H01L27/11517 ,  H01L27/11563

Abstract: A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.

公开(公告)号：US11568323B2

公开(公告)日：2023-01-31

申请号：US16650083

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava Prasad Nagaraja ,  Dae-hyun Kim ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06N3/04 ,  G06N20/10 ,  G06N3/08

Abstract: Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.

公开(公告)号：US11675997B2

公开(公告)日：2023-06-13

申请号：US16163772

申请日：2018-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava Prasad ,  Dae-hyun Kim ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06N3/04 ,  G06F17/15 ,  G06F21/52 ,  G06F12/06 ,  G06N5/04 ,  G06N3/063 ,  G06N5/046 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06F12/06 ,  G06F17/15 ,  G06F21/52 ,  G06N3/045 ,  G06N3/063 ,  G06N5/046

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network. The apparatus may include a memory, and a processor configured to read, from the memory, one of divided blocks of input data stored in a memory; generate an output block by performing the convolution operation on the one of the divided blocks with a kernel; generate a feature map by using the output block, and write the feature map to the memory.

公开(公告)号：US20190114542A1

公开(公告)日：2019-04-18

申请号：US16031565

申请日：2018-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-hoon Kim ,  Young-hwan Park ,  Dong-kwan Suh ,  Keshava Prasad Nagaraja ,  Dae-hyun Kim ,  Suk-jin Kim ,  Han-su Cho ,  Hyun-jung Kim

IPC: G06N3/08 ,  G06N3/063

Abstract: An electronic apparatus and method thereof are provided for performing deep learning. The electronic apparatus includes a storage configured to store target data and kernel data; and a processor including a plurality of processing elements that are arranged in a matrix shape. The processor is configured to input, to each of the plurality of processing elements, a first non-zero element from among a plurality of first elements included in the target data, and sequentially input, to each of a plurality of first processing elements included in a first row from among the plurality of processing elements, a second non-zero element from among the plurality of elements included in the kernel data. Each of the plurality of first processing elements is configured to perform an operation between the input first non-zero element and the input second non-zero element, based on depth information of the first non-zero element and depth information of the second non-zero element.