公开(公告)号：US20220173044A1

公开(公告)日：2022-06-02

申请号：US17674900

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20220068785A1

公开(公告)日：2022-03-03

申请号：US17324569

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.