公开(公告)号：US20220189916A1

公开(公告)日：2022-06-16

申请号：US17398406

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： YANGGYOO JUNG ,  Sungeun KIM ,  SANGMIN YONG ,  HAE-JUNG YU

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/64

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

公开(公告)号：US20210005553A1

公开(公告)日：2021-01-07

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20220173044A1

公开(公告)日：2022-06-02

申请号：US17674900

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20240243050A1

公开(公告)日：2024-07-18

申请号：US18503690

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-JUNG YU

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49822 ,  H01L22/32 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: A semiconductor package includes a package substrate, an interposer disposed on the package substrate, and a first semiconductor chip disposed on the interposer. The interposer includes a first semiconductor substrate and a first dielectric layer disposed on the first semiconductor substrate. The first dielectric layer includes a first scribe lane region. The first scribe lane region is below the first semiconductor chip along a first direction that is perpendicular to a top surface of the first semiconductor substrate. The first scribe lane region is spaced apart from a lateral surface of the interposer.

公开(公告)号：US20240404984A1

公开(公告)日：2024-12-05

申请号：US18805223

申请日：2024-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-JUNG YU

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.

公开(公告)号：US20220328445A1

公开(公告)日：2022-10-13

申请号：US17646672

申请日：2021-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-JUNG YU

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.