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    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE
    2.
    发明公开
    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE 审中-公开

    公开(公告)号：US20230290718A1

    公开(公告)日：2023-09-14

    申请号：US18199824

    申请日：2023-05-19

    申请人： Samsung Electronics Co., Ltd.

    发明人： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

    IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/31

    CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816

    摘要： Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220352309A1

    公开(公告)日：2022-11-03

    申请号：US17714695

    申请日：2022-04-06

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： JINBUM KIM ,  DAHYE KIM ,  DONGMYOUNG KIM ,  DONGWOO KIM ,  YONGJUN NAM ,  SANGMOON LEE ,  INGYU JANG ,  SUJIN JUNG

    IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10

    摘要： A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE
    4.
    发明申请
    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE 有权

    公开(公告)号：US20220068785A1

    公开(公告)日：2022-03-03

    申请号：US17324569

    申请日：2021-05-19

    申请人： Samsung Electronics Co., Ltd.

    发明人： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

    IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/48

    摘要： Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240234551A1

    公开(公告)日：2024-07-11

    申请号：US18539355

    申请日：2023-12-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jangwoo PARK ,  DONGWOO KIM ,  JINBUM KIM

    IPC分类号： H01L29/732 ,  H01L23/522

    CPC分类号： H01L29/732 ,  H01L23/522 ,  H01L29/0673

    摘要： A semiconductor device includes first, second, and third epitaxial layers sequentially stacked on a substrate and a first diffusion prevention layer provided in at least one of regions between the first and second epitaxial layers and between the second and third epitaxial layers. The first and third epitaxial layers have a first conductivity type, and the second epitaxial layer has a second conductivity type. The first diffusion prevention layer is configured to prevent an impurity in the second epitaxial layer from being diffused. The first, second, and third epitaxial layers include first, second, and third active patterns, respectively, which are respective provided in upper portions thereof and on collector, base, and emitter regions, respectively, of the substrate.