公开(公告)号：US20200020647A1

公开(公告)日：2020-01-16

申请号：US16198978

申请日：2018-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG KUN JEE ,  JI HWANG KIM ,  UN BYOUNG KANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/29

Abstract: A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.

公开(公告)号：US20210005553A1

公开(公告)日：2021-01-07

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20170005075A1

公开(公告)日：2017-01-05

申请号：US15168236

申请日：2016-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoo LEE ,  Minsoo KIM ,  Teak Hoon LEE ,  YOUNG KUN JEE

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the package substrate and a second surface that is opposite to the first surface, a second semiconductor chip stacked on the first semiconductor chip that includes a third surface facing the first semiconductor chip and a fourth surface that is opposite to the third surface, and an integral adhesive structure that substantially continuously fills a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips. The integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips. The extension has one continuously convex sidewall between a level of the first surface and a level of the fourth surface.

Abstract translation: 半导体封装包括堆叠在封装基板上的第一半导体芯片，其中第一半导体芯片的第一表面面向封装基板和与第一表面相对的第二表面，堆叠在第一半导体芯片上的第二半导体芯片， 包括面向所述第一半导体芯片的第三表面和与所述第三表面相对的第四表面，以及整体粘合剂结构，其基本上连续地填充所述封装衬底和所述第一半导体芯片之间的第一空间，以及第一空间， 第二个半导体芯片。 整体粘合结构包括从第一和第二半导体芯片的外侧壁突出的延伸部。 该延伸部在第一表面的高度和第四表面的高度之间具有一个连续的凸起的侧壁。

公开(公告)号：US20240105679A1

公开(公告)日：2024-03-28

申请号：US18135035

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  SANGHOON LEE ,  UN-BYOUNG KANG ,  SANG CHEON PARK ,  JUMYONG PARK ,  HYUNCHUL JUNG

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03 ,  H01L2224/08146 ,  H01L2225/06541

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.

公开(公告)号：US20220173044A1

公开(公告)日：2022-06-02

申请号：US17674900

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20130330925A1

公开(公告)日：2013-12-12

申请号：US13893449

申请日：2013-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hong MIN ,  CHAJEA JO ,  Taeje CHO ,  YOUNG KUN JEE

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/68 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Disclosed are methods of treating a device-substrate, and support-substrates used therein. The methods may include providing the device-substrate having an integrated circuit, bonding a first top surface of the device-substrate to a support-substrate, and polishing a first bottom surface of the device-substrate. The support-substrates include a second top surface, a second bottom surface opposite to the second top surface, and a sidewall connecting the second top and bottom surfaces. Additionally, the support-substrates further include a grooved portion spaced apart from the sidewall and blocking a crack in the support-substrates occurring from the sidewall.

Abstract translation: 公开了处理器件衬底和其中使用的支撑衬底的方法。 所述方法可以包括提供具有集成电路的器件衬底，将器件衬底的第一顶表面接合到支撑衬底，以及抛光器件衬底的第一底表面。 支撑基板包括第二顶表面，与第二顶表面相对的第二底表面和连接第二顶表面和底表面的侧壁。 此外，支撑基板还包括与侧壁间隔开的凹槽部分，并且阻挡从侧壁发生的支撑基板中的裂纹。