公开(公告)号：US20210028146A1

公开(公告)日：2021-01-28

申请号：US16854452

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20240332255A1

公开(公告)日：2024-10-03

申请号：US18742838

申请日：2024-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20230253363A1

公开(公告)日：2023-08-10

申请号：US18133959

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  JIHOON KIM ,  JiHwan SUH ,  SO YOUN LEE ,  JIHWAN HWANG ,  TAEHUN KIM ,  JI-SEOK HONG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/80 ,  H01L25/18 ,  H01L24/08 ,  H01L21/565 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2224/08146 ,  H01L2224/80896 ,  H01L2224/80895

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

公开(公告)号：US20230290718A1

公开(公告)日：2023-09-14

申请号：US18199824

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

公开(公告)号：US20220068785A1

公开(公告)日：2022-03-03

申请号：US17324569

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.