公开(公告)号：US11689224B2

公开(公告)日：2023-06-27

申请号：US17199803

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunae Lee ,  Kijun Lee ,  Yeonggeol Song ,  Myungkyu Lee ,  Seokha Hwang

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/1575 ,  G06F11/1076 ,  H03M13/1525

Abstract: An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

公开(公告)号：US11631448B1

公开(公告)日：2023-04-18

申请号：US17244466

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae Lee ,  Sunghye Cho ,  Kijun Lee ,  Junjin Kong ,  Yeonggeol Song

IPC: G11C11/406 ,  G06F12/06

Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

公开(公告)号：US11106535B2

公开(公告)日：2021-08-31

申请号：US16926000

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kijun Lee ,  Yeonggeol Song ,  Sungrae Kim ,  Chanki Kim ,  Myungkyu Lee ,  Sanguhn Cha

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/00

Abstract: An error correction circuit includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page as a read codeword based on an externally provided address to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.