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    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS 有权

    公开(公告)号：US20230119555A1

    公开(公告)日：2023-04-20

    申请号：US17736154

    申请日：2022-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

    IPC: G06F11/10 ,  G06F11/07 ,  H03M13/11

    Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220405165A1

    公开(公告)日：2022-12-22

    申请号：US17535762

    申请日：2021-11-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Sunggi Ahn ,  Yesin Ryu ,  Sukhan Lee

    IPC: G06F11/10 ,  G11C29/04

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

    Memory systems and controllers for generating a command address and methods of operating same
    4.
    发明授权
    Memory systems and controllers for generating a command address and methods of operating same 有权

    公开(公告)号：US12235757B2

    公开(公告)日：2025-02-25

    申请号：US18318906

    申请日：2023-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

    IPC: G06F11/10 ,  G06F12/06

    Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

    SEMICONDUCTOR MEMORY DEVICES
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20240370335A1

    公开(公告)日：2024-11-07

    申请号：US18778475

    申请日：2024-07-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  KIJUN LEE ,  MYUNGKYU LEE ,  YEONGGEOL SONG ,  Jinhoon Jang ,  SUNGHYE CHO ,  Isak Hwang

    IPC: G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

    SEMICONDUCTOR MEMORY DEVICES
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230367672A1

    公开(公告)日：2023-11-16

    申请号：US18226622

    申请日：2023-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

    IPC: G06F11/10

    CPC classification number: G06F11/1068

    Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES
    8.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230168819A1

    公开(公告)日：2023-06-01

    申请号：US17842981

    申请日：2022-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

    Error correction circuit, memory system, and error correction method
    9.
    发明授权
    Error correction circuit, memory system, and error correction method 有权

    公开(公告)号：US12212339B2

    公开(公告)日：2025-01-28

    申请号：US17984430

    申请日：2022-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungkyu Lee ,  Kijun Lee ,  Sunghye Cho ,  Sungrae Kim

    IPC: H03M13/15 ,  H03M13/00

    Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

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