公开(公告)号：US20240250031A1

公开(公告)日：2024-07-25

申请号：US18594816

申请日：2024-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Sanghyun Lee ,  Hakyoon Ahn ,  Seonghan Oh ,  Youngmook Oh

IPC: H01L23/532 ,  H01L21/308 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L23/53295 ,  H01L21/3083 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76846 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/0629 ,  H01L27/088 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

公开(公告)号：US11948888B2

公开(公告)日：2024-04-02

申请号：US17338787

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Sanghyun Lee ,  Hakyoon Ahn ,  Seonghan Oh ,  Youngmook Oh

IPC: H01L23/532 ,  H01L21/308 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L49/02 ,  H01L29/165

CPC classification number: H01L23/53295 ,  H01L21/3083 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76846 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/0629 ,  H01L27/088 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

公开(公告)号：US20230128547A1

公开(公告)日：2023-04-27

申请号：US18087854

申请日：2022-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Sungwoo Kang ,  Jongchul Park ,  Youngmook Oh ,  Jeongyun Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45

Abstract: An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

公开(公告)号：US20230097668A1

公开(公告)日：2023-03-30

申请号：US18050219

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Sungwoo Kang ,  Jongchul Park ,  Youngmook Oh ,  Jeongyun Lee

IPC: H01L27/088 ,  H01L29/417 ,  H01L21/768

Abstract: A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

公开(公告)号：US11488952B2

公开(公告)日：2022-11-01

申请号：US16888209

申请日：2020-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghyun Lee ,  Sungwoo Kang ,  Jongchul Park ,  Youngmook Oh ,  Jeongyun Lee

IPC: H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

公开(公告)号：US20190229062A1

公开(公告)日：2019-07-25

申请号：US16167717

申请日：2018-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik Shin ,  Sanghyun Lee ,  Hakyoon Ahn ,  Seonghan Oh ,  Youngmook Oh

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088

Abstract: A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.

公开(公告)号：US10332898B2

公开(公告)日：2019-06-25

申请号：US15635583

申请日：2017-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.