公开(公告)号：US11749734B2

公开(公告)日：2023-09-05

申请号：US18087854

申请日：2022-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Sungwoo Kang ,  Jongchul Park ,  Youngmook Oh ,  Jeongyun Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

公开(公告)号：US11869811B2

公开(公告)日：2024-01-09

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/0886

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US11735627B2

公开(公告)日：2023-08-22

申请号：US17324610

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon Park ,  Jongchul Park ,  Bokyoung Lee ,  Jeongyun Lee ,  Hyunggoo Lee ,  Yeondo Jung ,  Haegeon Jung

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/0657 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

公开(公告)号：US10366927B2

公开(公告)日：2019-07-30

申请号：US15405420

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US11211294B2

公开(公告)日：2021-12-28

申请号：US16503728

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US10192966B2

公开(公告)日：2019-01-29

申请号：US15692560

申请日：2017-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunho Jung ,  Jeongyun Lee ,  Taesoon Kwon ,  Kyungseok Min ,  Geumjung Seong ,  Bora Lim ,  A-Reum Ji ,  Seungsoo Hong

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device can include a first active pattern on a substrate, the first active pattern including a plurality of first active regions that protrude from the substrate. A second active pattern can be on the substrate including a plurality of second active regions that protrude from the substrate. A first gate electrode can include an upper portion that extends over the first active pattern at a first height and include a recessed portion that extends over the first active pattern at a second height that is lower than the first height of the first gate electrode. A second gate electrode can include an upper portion that extends over the second active pattern at a first height and include a recessed portion that extends over the second active pattern at a second height that is lower than the first height of the second gate electrode. An insulation pattern can be located between, and directly adjacent to, the recessed portion of the first gate electrode and the recessed portion of the second gate electrode, the insulation pattern electrically isolating the first and second gate electrodes from one another.

公开(公告)号：US20230128547A1

公开(公告)日：2023-04-27

申请号：US18087854

申请日：2022-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Sungwoo Kang ,  Jongchul Park ,  Youngmook Oh ,  Jeongyun Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45

Abstract: An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

公开(公告)号：US20230097668A1

公开(公告)日：2023-03-30

申请号：US18050219

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Sungwoo Kang ,  Jongchul Park ,  Youngmook Oh ,  Jeongyun Lee

IPC: H01L27/088 ,  H01L29/417 ,  H01L21/768

Abstract: A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

公开(公告)号：US11488952B2

公开(公告)日：2022-11-01

申请号：US16888209

申请日：2020-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghyun Lee ,  Sungwoo Kang ,  Jongchul Park ,  Youngmook Oh ,  Jeongyun Lee

IPC: H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

公开(公告)号：US09673279B2

公开(公告)日：2017-06-06

申请号：US15208007

申请日：2016-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongyun Lee ,  Kwang-Yong Yang ,  Keomyoung Shin ,  Jinwook Lee ,  Yongseok Lee

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/1033 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.