公开(公告)号：US20180322932A1

公开(公告)日：2018-11-08

申请号：US15585680

申请日：2017-05-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kirubakaran Periyannan ,  Daniel Joseph Linnen

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C16/14

CPC classification number: G11C16/3427 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459

Abstract: Techniques are presented for the prevention and detection of inter-plane disturbs in a memory circuit, where, when concurrently performing memory operations on multiple planes, a defect in one plane can feed back through a common supply node and adversely affect memory operations in another node. To isolate such defects to plane in which the occur, the memory supplies the elements, such as a word line, of different planes from a common supply node through a uni-directional circuit element, such as a diode. In this way, if the voltage on an element in an array gets pulled up to an elevated voltage though a defect, this elevated voltage is stopped from flowing back to the common supply node. Additionally, by comparing the voltage levels on either side of the uni-directional circuit element, it can be determined whether such a defect is present in an array.