公开(公告)号：US07957205B2

公开(公告)日：2011-06-07

申请号：US12574413

申请日：2009-10-06

申请人： Hiroaki Wada ,  Kazuhiro Kurihara

发明人： Hiroaki Wada ,  Kazuhiro Kurihara

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C5/147 ,  H04N5/23241

摘要： The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

公开(公告)号：US07606085B2

公开(公告)日：2009-10-20

申请号：US11501449

申请日：2006-08-08

申请人： Hiroaki Wada ,  Kazuhiro Kurihara

发明人： Hiroaki Wada ,  Kazuhiro Kurihara

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C5/147 ,  H04N5/23241

摘要： The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

摘要翻译： 本发明是一种半导体器件，包括：串联连接在电源Vcc（第一电源）和地（第二电源）之间的电阻器R11（第一电阻器部分）和FET 15（第二电阻器部件）; 输出节点N11，设置在电阻器R11和FET15之间，用于输出参考电压; 设置在电源Vcc和地之间的反馈节点N12; 以及通过使用输出节点N11的参考电压和反馈节点N12的电压将反馈节点N12的电压维持在恒定电平的电压控制电路（19）。 本发明可以提供一种具有能够产生不依赖于电源电压的参考电压的参考电压产生电路及其控制方法的半导体器件。

公开(公告)号：US07606068B2

公开(公告)日：2009-10-20

申请号：US12017693

申请日：2008-01-22

申请人： Ming-Huei Shieh ,  Kazuhiro Kurihara

发明人： Ming-Huei Shieh ,  Kazuhiro Kurihara

IPC分类号： G11C11/34

CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2211/5634

摘要： A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).

摘要翻译： 一种具有在存储器核心（401）上制造的双位动态参考架构（408,410）的基于核心的多位存储器（400）。 在存储器核心（401）上制造第一参考阵列（408）和第二参考阵列（410），使得包括第一参考阵列（408）的一个单元（182）的参考单元对（185）和相应的 对第二参考阵列（410）的单元（184）进行读取和平均以提供用于读取数据阵列的参考电压。

公开(公告)号：US07573743B2

公开(公告)日：2009-08-11

申请号：US11514391

申请日：2006-08-30

申请人： Hiroki Murakami ,  Kazuhiro Kurihara

发明人： Hiroki Murakami ,  Kazuhiro Kurihara

IPC分类号： G11C11/34

CPC分类号： G11C11/413 ,  G11C16/102 ,  G11C16/105

摘要： A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

摘要翻译： 一种半导体器件包括：具有全部要被擦除并具有闪存单元的数据的第一扇区（12）; 具有全部要保留并具有闪存单元的数据的第二扇区（14）; 扇区选择电路（16）在擦除第一扇区中的数据期间从扇区中选择一对扇区，所述一对扇区是第一扇区和第二扇区; 以及保持第二扇区的数据的SRAM阵列（存储）（30）。 本发明可以提供一种半导体器件，其中使用了减少数量的扇区选择电路，使得可以减小存储单元阵列的面积并提供一种控制半导体器件的方法。

公开(公告)号：US07450434B2

公开(公告)日：2008-11-11

申请号：US11127713

申请日：2005-05-12

申请人： Yasuhiko Tanuma ,  Kazuhiro Kurihara

发明人： Yasuhiko Tanuma ,  Kazuhiro Kurihara

IPC分类号： G11C11/34

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/16

摘要： A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.

摘要翻译： 半导体器件包括具有连接到本地字线的存储器单元的扇区，选择扇区的解码器，以及在擦除所选择的扇区时产生使与选择的扇区相关联的解码器中的对应的一个解码器暂时地产生的控制信号的电路 未选择 每个扇区包括一个上拉晶体管，该上拉晶体管经由相应的解码器之一经由连接扇区的全局字线对应的一个驱动本地字线之一，并且上拉晶体管由 控制信号。

公开(公告)号：US20080159011A1

公开(公告)日：2008-07-03

申请号：US11986385

申请日：2007-11-20

申请人： Kazuhiro Kurihara ,  Nobutaka Taniguchi

发明人： Kazuhiro Kurihara ,  Nobutaka Taniguchi

IPC分类号： G11C7/10

CPC分类号： G11C5/066 ,  G11C7/1045 ,  G11C7/1078

摘要： The present invention provides a semiconductor device and a method of controlling the semiconductor device, the semiconductor device comprising: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal comprising: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is comprised of the entire remaining portion of the address data not comprising the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address data to the other one of the first internal address line or the second internal address line, when the address data is input to the terminal.

摘要翻译： 本发明提供一种半导体器件及其控制方法，所述半导体器件包括：存储单元阵列; 输入或输出存储在存储单元阵列中的存储数据的终端，并且输入指示存储单元阵列中存​​储数据被输入或输出的地址的地址数据，该终端包括：第一终端，其输入第一部分 地址数据; 以及输入所述地址数据的第二部分的第二终端，其中所述地址数据的第二部分包括不包括所述地址数据的第一部分的地址数据的整个剩余部分; 提供地址数据的第一内部地址线和第二内部地址线; 以及根据预定的开关信息将地址数据的第一部分耦合到第一内部地址线或第二内部地址线之一的开关，同时将第二部分地址数据耦合到第一内部地址线中的另一个 地址线或第二个内部地址线，当地址数据输入终端时。

公开(公告)号：US07324374B2

公开(公告)日：2008-01-29

申请号：US10600065

申请日：2003-06-20

申请人： Ming-Huei Shieh ,  Kazuhiro Kurihara

发明人： Ming-Huei Shieh ,  Kazuhiro Kurihara

IPC分类号： G11C11/34

CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2211/5634

摘要： A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).

摘要翻译： 一种具有在存储器核心（401）上制造的双位动态参考架构（408,410）的基于核心的多位存储器（400）。 在存储器核心（401）上制造第一参考阵列（408）和第二参考阵列（410），使得包括第一参考阵列（408）的一个单元（182）的参考单元对（185）和相应的 对第二参考阵列（410）的单元（184）进行读取和平均以提供用于读取数据阵列的参考电压。

公开(公告)号：US07307894B2

公开(公告)日：2007-12-11

申请号：US11127712

申请日：2005-05-12

申请人： Kazunari Kido ,  Kazuhiro Kurihara ,  Minoru Yamashita

发明人： Kazunari Kido ,  Kazuhiro Kurihara ,  Minoru Yamashita

IPC分类号： G11C7/10

CPC分类号： G11C16/22 ,  G11C15/00 ,  G11C15/04

摘要： The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.

摘要翻译： 半导体器件包括：存储单元阵列，其包括用于存储数据的存储单元，并以扇区为基础进行管理;存储器，其存储确定激活状态的信息;锁存电路，其根据存储在存储器中的信息来锁存激活信息 以及根据存储在锁存电路中的存储器中的信息来锁存激活信息的电路。 根据存储器的存储状态的激活信息在激活之后输入给定命令时被锁存，因此可以读取存储在存储器中的信息，并且可靠地设置锁存电路中的信息。

公开(公告)号：US07180785B2

公开(公告)日：2007-02-20

申请号：US11085496

申请日：2005-03-22

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C8/08 ,  G11C8/12 ,  G11C16/08

摘要： A nonvolatile semiconductor memory device is disclosed that comprises plural sectors each including a memory cell array, plural word line drivers provided in each one of the sectors to drive respective word lines, and sector switches provided one for each sector. The sector switches are connected to the plural word line drivers in the corresponding sector, adapted to provide a negative voltage to be applied to the word lines to the plural word line drivers when the corresponding sector is selected for an erase operation. The sector switches only include transistors directly connected to an output signal line to provide the negative voltage to the word line drivers. A decoding circuit shared by one or more sectors is adapted to control the sector switches to allow a sector switch in a selected sector to output the negative voltage and allow a sector switch in an unselected sector to output a voltage different from the negative voltage.

摘要翻译： 公开了一种非易失性半导体存储器件，其包括多个扇区，每个扇区各自包括存储单元阵列，设置在每个扇区中的多个字线驱动器以驱动相应的字线，以及为每个扇区提供一个扇区开关。 扇区开关连接到相应扇区中的多个字线驱动器，适于在为擦除操作选择相应的扇区时提供要施加到多个字线驱动器的字线的负电压。 扇区开关仅包括直接连接到输出信号线的晶体管，以向字线驱动器提供负电压。 由一个或多个扇区共享的解码电路适于控制扇区开关以允许所选扇区中的扇区切换输出负电压并允许未选择扇区中的扇区切换输出不同于负电压的电压。

公开(公告)号：US20070030740A1

公开(公告)日：2007-02-08

申请号：US11501449

申请日：2006-08-08

申请人： Hiroaki Wada ,  Kazuhiro Kurihara

发明人： Hiroaki Wada ,  Kazuhiro Kurihara

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C5/147 ,  H04N5/23241

摘要： The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

摘要翻译： 本发明是一种半导体器件，包括：串联连接在电源Vcc（第一电源）和地（第二电源）之间的电阻器R11（第一电阻器部分）和FET 15（第二电阻器部件）; 输出节点N11，设置在电阻器R11和FET15之间，用于输出参考电压; 设置在电源Vcc和地之间的反馈节点N12; 以及通过使用输出节点N11的参考电压和反馈节点N12的电压将反馈节点N12的电压维持在恒定电平的电压控制电路（19）。 本发明可以提供一种具有能够产生不依赖于电源电压的参考电压的参考电压产生电路及其控制方法的半导体器件。