公开(公告)号：US07978534B2

公开(公告)日：2011-07-12

申请号：US12498988

申请日：2009-07-07

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： G11C7/00

CPC分类号： G11C11/413 ,  G11C8/06 ,  G11C8/12

摘要： A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register.

摘要翻译： 存储器设备包括可配置地址寄存器，其具有耦合到第一组地址总线端子的第一组输入缓冲器和耦合到第二组地址总线端子的第二组输入缓冲器。 在第一寻址配置中，地址信号被同时施加到第一和第二组中的地址总线端子，并且它们被同时存储在相应的地址寄存器中。 在第二寻址配置中，多组地址信号仅在第一组地址总线端子中顺序地施加到地址总线端子。 然后将每组地址信号存储在不同的地址寄存器中。

公开(公告)号：US20110138252A1

公开(公告)日：2011-06-09

申请号：US13026833

申请日：2011-02-14

申请人： J. Thomas Pawlowski ,  John Schreck

发明人： J. Thomas Pawlowski ,  John Schreck

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

摘要： A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

摘要翻译： DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。 当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。 每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。 在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。 可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

公开(公告)号：US07900120B2

公开(公告)日：2011-03-01

申请号：US11583198

申请日：2006-10-18

申请人： J. Thomas Pawlowski ,  John Schreck

发明人： J. Thomas Pawlowski ,  John Schreck

IPC分类号： G11C29/00

CPC分类号： H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

摘要： A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

摘要翻译： DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。 当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。 每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。 在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。 可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

公开(公告)号：US07894289B2

公开(公告)日：2011-02-22

申请号：US11546692

申请日：2006-10-11

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： G11C7/00 ,  H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

摘要翻译： DRAM存储器件包括几组存储器单元，每个存储单元被分成第一组和第二组存储器单元。 可以以相对较慢的速率刷新第一组中的存储器单元以减少DRAM器件消耗的功率。 DRAM设备中的错误检查和校正电路校正由相对较慢的刷新率引起的第一组存储器单元中的任何数据保留错误。 第二组中的存储单元以正常速率刷新，速度足够快，不会发生数据保留错误。 可以对DRAM装置中的模式寄存器进行编程，以选择第二组存储器单元的大小。

公开(公告)号：US20100175130A1

公开(公告)日：2010-07-08

申请号：US12350132

申请日：2009-01-07

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： G06F21/00

CPC分类号： G06N5/025 ,  G06F7/02 ,  G06F2207/025 ,  G06K9/62

摘要： Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a matching-data reporting module, which may have a buffer and a match event table. The buffer may be coupled to a data stream and configured to store at least part of the data stream, and the match event table may be configured to store data indicative of a buffer location corresponding with a start of a search criterion being satisfied.

摘要翻译： 公开了方法和装置，其中包括模式识别处理器的装置。 模式识别处理器可以包括匹配数据报告模块，其可以具有缓冲器和匹配事件表。 缓冲器可以耦合到数据流并且被配置为存储数据流的至少一部分，并且匹配事件表可以被配置为存储指示与满足搜索条件的开始相对应的缓冲器位置的数据。

公开(公告)号：US20090154228A1

公开(公告)日：2009-06-18

申请号：US12371856

申请日：2009-02-16

申请人： J. Thomas Pawlowski ,  Patricia C. Elkins

发明人： J. Thomas Pawlowski ,  Patricia C. Elkins

IPC分类号： G11C11/00 ,  G11C11/416

CPC分类号： G11C7/1006 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

摘要： An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has that data state, such matching data states are identified and writing to those bits is precluded during the write command. In one embodiment, both the incoming data to be written to a bit and the data currently present at that bit address are latched. These latched data are then compared (e.g., with an XOR gate) to determine which bits have a matching data state. The results of this comparison are used as an enable signal to the write (column) driver in the PCRAM memory array, with the effect that only data bits having different data state are written, while data bits having a matching data state are not needlessly re-written. Because matching data states are ignored, reliability problems associated with such redundant writing are alleviated, and power is saved.

摘要翻译： 公开了用于操作PCRAM集成电路的改进的架构和方法，其尝试最小化电池中的相变材料的电阻的劣化。 当在写入命令期间尝试将数据状态写入已经具有该数据状态的位时，识别这种匹配数据状态，并且在写入命令期间排除对这些位的写入。 在一个实施例中，要写入位的输入数据和当前存在于该位地址处的数据都被锁存。 然后比较这些锁存的数据（例如，与异或门），以确定哪些位具有匹配的数据状态。 该比较的结果用作对PCRAM存储器阵列中的写入（列）驱动器的使能信号，其效果是仅写入具有不同数据状态的数据位，而具有匹配数据状态的数据位不必要地重新 -书面。 由于忽略了匹配的数据状态，因此可以减轻与这种冗余写入相关的可靠性问题，节省电力。

公开(公告)号：US20080109705A1

公开(公告)日：2008-05-08

申请号：US11583198

申请日：2006-10-18

申请人： J. Thomas Pawlowski ,  John Schreck

发明人： J. Thomas Pawlowski ,  John Schreck

IPC分类号： G11C29/00

CPC分类号： H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

摘要： A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

摘要翻译： DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。 当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。 每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。 在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。 可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

公开(公告)号：US20080092016A1

公开(公告)日：2008-04-17

申请号：US11546692

申请日：2006-10-11

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

摘要翻译： DRAM存储器件包括几组存储器单元，每个存储单元被分成第一组和第二组存储器单元。 可以以相对较慢的速率刷新第一组中的存储器单元以减少DRAM器件消耗的功率。 DRAM设备中的错误检查和校正电路校正由相对较慢的刷新率引起的第一组存储器单元中的任何数据保留错误。 第二组中的存储单元以正常速率刷新，速度足够快，不会发生数据保留错误。 可以对DRAM装置中的模式寄存器进行编程，以选择第二组存储器单元的大小。

公开(公告)号：US06385687B2

公开(公告)日：2002-05-07

申请号：US09312122

申请日：1999-05-14

申请人： J. Thomas Pawlowski ,  Joel Watkins

发明人： J. Thomas Pawlowski ,  Joel Watkins

IPC分类号： G06F1200

CPC分类号： G06F12/0879 ,  G06F12/0855

摘要： A memory device includes a data array, a tag array, and control logic. The data array is adapted to store a plurality of data array entries. The tag array is adapted to store a plurality of data array entries corresponding to the data array entries. The control logic adapted to access a subset of the data array entries in the data array using a burst access and to access the tag array during the burst access. A method for accessing a memory device is provided. The memory device includes a data array and a tag array. The method includes receiving a data array burst access command. The data array is accessed in response to the data array burst access command. A tag array access is received. The tag array is accessed in response to the tag array access command while the data array is being accessed.

摘要翻译： 存储器件包括数据阵列，标签阵列和控制逻辑。 数据阵列适于存储多个数据阵列条目。 标签阵列适于存储对应于数据阵列条目的多个数据阵列条目。 所述控制逻辑适于使用脉冲串访问来访问所述数据阵列中的所述数据阵列条目的子集，并且在所述突发存取期间访问所述标签阵列。 提供了一种访问存储器件的方法。 存储器件包括数据阵列和标签阵列。 该方法包括接收数据阵列突发存取命令。 响应于数据阵列突发存取命令访问数据阵列。 接收到标签数组访问。 在访问数据数组时，会对tag数组访问命令进行访问。

公开(公告)号：US06185656B2

公开(公告)日：2001-02-06

申请号：US09516592

申请日：1999-07-09

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： G06F1314

CPC分类号： G11C7/1039 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/419

摘要： A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean function of the chip enable signals; an enable register having an input connected to the chip enable and select logic for temporarily storing the SRAM core enable signal, and having an output; a pipelined enable register coupled between the enable register and the SRAM core for temporarily storing the SRAM core enable signal and delaying propagation of the core enable signal to the SRAM core; and pipelining logic coupled to at least one of the three chip enable inputs to permit pipelining operation of the synchronous burst SRAM device.

摘要翻译： 包括具有存储器阵列的SRAM核心，写入驱动器，读出放大器和I / O缓冲器的同步突发SRAM器件; 用于接收SRAM核心中的存储器阵列的地址的地址寄存器; 连接到所述地址寄存器的突发地址发生器，用于使用存储在所述地址寄存器中的至少一个地址位来快速产生附加地址; 用于接收指示外部地址准备好被加载到地址寄存器中的外部地址信号的输入; 三芯片使能输入用于接收芯片使能信号; 芯片使能和选择逻辑耦合到三个芯片使能输入以执行以下双重任务：（1）选择性地启用或禁用同步脉冲串SRAM器件;以及（2）当SRAM器件根据 芯片使能信号在三芯片使能输入端的布尔函数，芯片使能和选择逻辑输出由芯片使能信号的布尔函数产生的SRAM内核使能信号; 使能寄存器具有连接到芯片使能和选择逻辑的输入，用于临时存储SRAM内核使能信号，并具有输出; 耦合在使能寄存器和SRAM内核之间的流水线使能寄存器，用于临时存储SRAM内核使能信号并延迟核心使能信号传播到SRAM内核; 以及耦合到三个芯片使能输入中的至少一个的流水线逻辑，以允许同步脉冲串SRAM设备的流水线操作。