公开(公告)号：US6069518A

公开(公告)日：2000-05-30

申请号：US352143

申请日：1994-12-01

申请人： Hiroaki Nakai ,  Shinichi Kobayashi ,  Motoharu Ishii ,  Atsushi Ohba ,  Tomoshi Futatsuya ,  Akira Hosogane

发明人： Hiroaki Nakai ,  Shinichi Kobayashi ,  Motoharu Ishii ,  Atsushi Ohba ,  Tomoshi Futatsuya ,  Akira Hosogane

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H02M3/07 ,  G05F1/10

CPC分类号： H02M3/073 ,  G11C16/30

摘要： In response to complementary clock signals provided from a driver, a charge pump operates to provide an output voltage which is a down-converted negative voltage. The voltage between this output voltage and a predetermined positive reference voltage is capacitance-divided by capacitors. The capacitance-divided positive voltage is applied to a comparator, whereby a reference voltage is compared with the above positive voltage. An output signal of the comparator is applied to the driver. In response, the driver controls the operation of the charge pump, whereby the output voltage is clamped at a predetermined voltage level for output.

摘要翻译： 响应于从驱动器提供的互补时钟信号，电荷泵操作以提供作为下变频负电压的输出电压。 该输出电压和预定的正参考电压之间的电压由电容器分压。 将电容分压正电压施加到比较器，由此将参考电压与上述正电压进行比较。 比较器的输出信号被施加到驱动器。 作为响应，驱动器控制电荷泵的操作，由此输出电压被钳位在预定的电压电平以便输出。

公开(公告)号：US06760259B1

公开(公告)日：2004-07-06

申请号：US10624599

申请日：2003-07-23

申请人： Tomoshi Futatsuya ,  Takashi Hayasaka ,  Taku Ogura

发明人： Tomoshi Futatsuya ,  Takashi Hayasaka ,  Taku Ogura

IPC分类号： G11C1616

CPC分类号： G11C16/08 ,  G11C16/16 ,  G11C16/344

摘要： Particular blocks are a boot block and parameter block having a storage capacity smaller than that of a general block. In the case where a boot block is not required, a signal BOOTE is set at an L level. In the case where a signal BLKSEL is at an H level in an erasure mode, a control unit selects four blocks aligned in a horizontal direction at the same time. The control unit also selects two blocks simultaneously in the vertical direction. As a result, the particular eight blocks are selected. The boot block and parameter block can be erased collectively as one block having a capacity similar to that of a general block. Therefore, a flash memory corresponding to the case of including a boot block and not including a boot block can be implemented simultaneously with one chip. Thus, the designing and fabrication process can be simplified.

摘要翻译： 特定块是具有比一般块的存储容量小的存储容量的引导块和参数块。 在不需要引导块的情况下，将信号BOOTE设定为L电平。 在擦除模式中信号BLKSEL处于H电平的情况下，控制单元同时选择沿水平方向排列的四个块。 控制单元同时在垂直方向上同时选择两个块。 结果，选择特定的八个块。 引导块和参数块可以被集体地擦除为具有与一般块相同的容量的一个块。 因此，可以与一个芯片同时实现与包括引导块并且不包括引导块的情况相对应的闪速存储器。 因此，可以简化设计和制造过程。

公开(公告)号：US5847994A

公开(公告)日：1998-12-08

申请号：US46672

申请日：1998-03-24

申请人： Akiko Motoshima ,  Tomoshi Futatsuya ,  Akira Okugaki

发明人： Akiko Motoshima ,  Tomoshi Futatsuya ,  Akira Okugaki

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C2216/22

摘要： In a flash memory, a reading bit line and a writing bit line are provided corresponding to a respective column of memory cells. A well voltage and a voltage on a source line can be controlled for each sub-block. Accordingly, data can be read at a sub-block while data can be written/erased at another sub-block, and therefore, the capacity ratio of a back ground operation region to the main memory region can be changed as desired.

摘要翻译： 在闪速存储器中，对应于相应列的存储器单元提供读取位线和写入位线。 可以对每个子块控制源极线上的阱电压和电压。 因此，可以在子块处读取数据，同时可以在另一个子块上写入/擦除数据，因此可以根据需要改变背景操作区域与主存储器区域的容量比。

公开(公告)号：US06831864B2

公开(公告)日：2004-12-14

申请号：US10601551

申请日：2003-06-24

申请人： Shinichi Mizoguchi ,  Tomoshi Futatsuya ,  Takashi Hayasaka

发明人： Shinichi Mizoguchi ,  Tomoshi Futatsuya ,  Takashi Hayasaka

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3468

摘要： A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on the memory transistors until the memory transistors are not in an overerased state.

公开(公告)号：US5999475A

公开(公告)日：1999-12-07

申请号：US34996

申请日：1998-03-05

申请人： Tomoshi Futatsuya ,  Atsushi Ohba

发明人： Tomoshi Futatsuya ,  Atsushi Ohba

IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C5/145

摘要： An internal potential generation circuit operates with the potential levels of an output node N.sub.H1 of a first boosting circuit and an output node N.sub.H2 of a second boosting circuit maintained in common in response to a high voltage switch circuit attaining a conductive state at the initial stage of the operation of the internal potential generation circuit. After the output potential level of the second boosting circuit arrives at a predetermined potential level, the high voltage switch circuit is cut off, whereby the first and second boosting circuits drive independently the potential level of corresponding output nodes.

摘要翻译： 内部电位产生电路与第一升压电路的输出节点NH1的电位电平和第二升压电路的输出节点NH2的电位相对应地响应于在初始阶段达到导通状态的高电压开关电路而保持共同 内部电位产生电路的运行。 在第二升压电路的输出电位达到预定电位后，高压开关电路被切断，由此第一和第二升压电路独立驱动相应的输出节点的电位。