公开(公告)号：US10275181B2

公开(公告)日：2019-04-30

申请号：US15863531

申请日：2018-01-05

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu ,  Yi-Da Chen

IPC: G06F3/06

Abstract: The invention introduces a method for scheduling and executing commands in a flash memory, performed by a processing unit, including at least the following steps: reading information stored in a command profile space to determine whether a priority command is present in a command queue; de-queuing the priority command from the command queue and executing the priority command when the priority command is present in the command queue; and using a scheduling algorithm to select a simple read/write command from the command queue and executing the simple read/write command when no priority command is present in the command queue.

公开(公告)号：US10169225B2

公开(公告)日：2019-01-01

申请号：US14604358

申请日：2015-01-23

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/10 ,  G06F13/16 ,  G11C16/34

Abstract: A memory system with a programming status is provided. The memory includes at least one first memory, at least one second memory and a controller. Each of the at least one first memory includes a plurality of memory regions to store data. Each of the at least one second memory includes a plurality of memory regions for programming the data from the at least one first memory. The controller is coupled to the second memory and utilized to record a programming status of the data. Whether the programming is successful or not is checked when the at least one first memory or the at least one second memory is going to be implemented by inquiring the programming status, and the at least one first memory stores the data until the programming is checked to be successful.

公开(公告)号：US20180341430A1

公开(公告)日：2018-11-29

申请号：US15863531

申请日：2018-01-05

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu ,  Yi-Da Chen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: The invention introduces a method for scheduling and executing commands in a flash memory, performed by a processing unit, including at least the following steps: reading information stored in a command profile space to determine whether a priority command is present in a command queue; de-queuing the priority command from the command queue and executing the priority command when the priority command is present in the command queue; and using a scheduling algorithm to select a simple read/write command from the command queue and executing the simple read/write command when no priority command is present in the command queue.

公开(公告)号：US09606733B2

公开(公告)日：2017-03-28

申请号：US14537551

申请日：2014-11-10

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/7205

Abstract: A data storage device includes a FLASH memory and a controller. The FLASH memory includes a plurality of blocks wherein each of the blocks includes a plurality of pages. The controller is coupled to the FLASH memory and utilized to execute a garbage-collection process on the FLASH memory according to a number of spare blocks in the FLASH memory and a number of inefficient blocks where most of the pages are spare in the FLASH memory. The garbage-collection process is utilized for merging at least two inefficient blocks to release at least one spare block from the inefficient blocks.

公开(公告)号：US12265468B2

公开(公告)日：2025-04-01

申请号：US18241996

申请日：2023-09-04

Applicant: Silicon Motion, Inc.

Inventor： Lu-Ting Wu ,  Shen-Ting Chiu ,  Te-Kai Wang ,  Po-Lin Wu

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/1009

Abstract: A method for performing access management of a memory device in a predetermined communications architecture with aid of automatic parameter setting and associated apparatus are provided. The method includes: utilizing the memory controller to set at least one write booster static parameter of a write booster function of the memory device; utilizing the memory controller to perform device initialization corresponding to at least one initialization phase of the memory device; and after completing the device initialization corresponding to the at least one initialization phase, performing at least one adaptive flag-setting operation, for setting at least one write booster flag among a plurality of write booster flags of the write booster function, wherein the at least one write booster flag includes a first write booster flag acting as a write booster switch. The adaptive flag-setting operation includes setting the first write booster flag to enable the write booster function by default.

公开(公告)号：US12210775B2

公开(公告)日：2025-01-28

申请号：US17984691

申请日：2022-11-10

Applicant: Silicon Motion, Inc.

Inventor： Lien-Yu Lee ,  Shen-Ting Chiu

IPC: G06F3/06

Abstract: The invention is related to an apparatus and a method for driving redundant array of independent disks (RAID) engine. The method, performed by a RAID controller in a RAID pre-processor, including: completing a driving operation for performing a series of physical-layer signal interactions with a RAID engine according to a driving value in the configuration register. The driving value corresponds to a command issued by a processing unit. The processing unit performs an operation irrelevant from an encoding or a decoding of a parity of a page group in parallel of the driving operation by the RAID controller in coordination with the RAID engine.

公开(公告)号：US12105622B2

公开(公告)日：2024-10-01

申请号：US18110747

申请日：2023-02-16

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F13/1668

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for data access in response to a host discard command. The method includes: allocating space in a random access memory (RAM) for an expanded discard table; receiving the host discard command from a host side; appending new entries each including one first logical address to the expanded discard table; and setting a start-address register and/or an end-address register in a performance engine for redefining an address range in the RAM that stores the expanded discard table, thereby enabling the performance engine to search the expanded discard table in the address range in the RAM for determining whether a specific logical address of user data is no longer used.

公开(公告)号：US11995224B2

公开(公告)日：2024-05-28

申请号：US17329175

申请日：2021-05-25

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F21/79 ,  G06F21/60 ,  G06F21/62

CPC classification number: G06F21/79 ,  G06F21/604 ,  G06F21/6209

Abstract: A memory controller coupled to a memory device and configured to control access operations of the memory device includes a data protection engine and a microprocessor. The data protection engine is configured to generate protection information according to data received from a host device. The microprocessor is configured to detect a status of the memory device in response to one or more write operations for writing the data to the memory device, determine whether a portion of the data has to be excluded when generating the protection information corresponding to the data according to the status and accordingly generate a determination result, and store the protection information and the determination result together in the memory device. The determination result indicates which portion of the data is utilized to generate the protection information.

公开(公告)号：US11308007B2

公开(公告)日：2022-04-19

申请号：US16854413

申请日：2020-04-21

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F13/16 ,  G06F12/02 ,  G06F12/0831 ,  G06F13/28 ,  G06F9/30 ,  G06F9/54

Abstract: The invention introduces a method for executing host input-output (IO) commands, performed by a processing unit of a device side when loading and executing program code of a first layer, at least including: receiving a slot bit table (SBT) including an entry from a second layer, where each entry is associated with an IO operation; receiving a plurality of addresses of callback functions from the second layer; and repeatedly executing a loop until IO operations of the SBT have been processed completely, and, in each iteration of the loop, calling the callback functions implemented in the second layer for a write operation or a read operation of the SBT to drive the frontend interface through the second layer.

公开(公告)号：US20210373800A1

公开(公告)日：2021-12-02

申请号：US17329189

申请日：2021-05-25

Applicant: Silicon Motion, Inc.

Inventor： Shen-Ting Chiu

IPC: G06F3/06

Abstract: A memory controller coupled to a memory device and a host device and configured to control access operations of the memory device includes a buffer memory, a host interface, a microprocessor and a data protection engine. The host interface is coupled to the host device and configured to write data received from the host device into the buffer memory and issue a buffer memory write complete notification after the data has been written in the buffer memory. The microprocessor is configured to trigger a data protection operation in response to the buffer memory write complete notification. The protection engine is configured to perform the data protection operation to generate corresponding protection information according to the data written in the buffer memory. The microprocessor is configured to directly trigger the data protection operation after confirming that the data has been written in the buffer memory.