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21.发明授权System and method for read migratory optimization in a cache coherency protocol 失效缓存一致性协议中读取迁移优化的系统和方法公开(公告)号：US07143245B2
公开(公告)日：2006-11-28
申请号：US10761044
申请日：2004-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0828 , G06F2212/2542
摘要： A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.
摘要翻译： 系统包括包括具有相关D状态的数据的第一节点和用于提供请求数据的源广播的第二节点。 第一节点响应于源广播而操作以向第二节点提供数据，并将与第一节点处的数据相关联的状态从D状态转换到O状态，而不同时更新存储器。 S状态与第二节点处的数据相关联。
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22.发明授权Method and apparatus for adaptively bypassing one or more levels of a cache hierarchy 有权用于自适应地绕过高速缓存层级的一个或多个级别的方法和装置公开(公告)号：US06647466B2
公开(公告)日：2003-11-11
申请号：US09769552
申请日：2001-01-25
申请人： Simon C. Steely, Jr.
发明人： Simon C. Steely, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0888 , G06F12/0891
摘要： A system for adaptively bypassing one or more higher cache levels following a miss in a lower level of a cache hierarchy is described. Each cache level preferably includes a tag store containing address and state information for each cache line resident in the respective cache. When an invalidate request is received at a given cache hierarchy, each cache level is searched for the address specified by the invalidate request. When an address match is detected, the state of the respective cache line is changed to the invalid state, although the address of the cache line is left in the tag store. Thereafter, if the processor or entity associated with this cache hierarchy issues its own request for this same cache line, the cache hierarchy begins searching the tag store of each level starting with the lowest cache level. Since the address of the invalidated cache line was left in the respective tag store, a match will be detected at one of the cache levels, although the corresponding state of this cache line is invalid. This condition is specifically detected and is considered to be an “inval_miss” occurrence. In response, to an inval_miss, the cache hierarchy calls off searching any higher levels, and instead, issues a memory reference request for the desired cache line. In a further embodiment, the entity that sourced an invalidate request is stored, and a subsequent memory reference request for the same cache line is sent directly to the source entity.
摘要翻译： 描述了用于在高速缓存层级的较低级别中错过之后自适应地绕过一个或多个更高的高速缓存级别的系统。 每个高速缓存级别优选地包括标签存储，其包含驻留在相应高速缓存中的每个高速缓存行的地址和状态信息。 当在给定的缓存层次结构中接收到无效请求时，将搜索每个高速缓存级别以查找由无效请求指定的地址。 当检测到地址匹配时，尽管高速缓存行的地址被留在标签存储器中，但各个高速缓存行的状态被改变为无效状态。 此后，如果与该高速缓存层级相关联的处理器或实体发出其对该相同高速缓存行的自身请求，则高速缓存层级开始以最低高速缓存级别开始搜索每个级别的标签存储。 由于无效高速缓存行的地址被留在相应的标签存储中，所以在高速缓存级别之一处将检测到匹配，尽管该高速缓存行的相应状态是无效的。 该条件被特别检测并被认为是“inval_miss”事件。 作为响应，对于inval_miss，缓存层次结构调用搜索任何更高级别，而是发出所需高速缓存行的内存引用请求。 在另一个实施例中，存储了源自无效请求的实体，并且将相同高速缓存行的后续存储器引用请求直接发送到源实体。
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公开(公告)号：US5283873A
公开(公告)日：1994-02-01
申请号：US546364
申请日：1990-06-29
CPC分类号： G06F9/3806
摘要： A next line prediction mechanism for predicting a next instruction index to an instruction cache of a computer pipeline, has a latency equal to the cycle time of the instruction cache to maximize the instruction bandwidth out of the instruction cache. The instruction cache outputs a block of instructions with each fetch initiated by a next instruction index provided by the line prediction mechanism. The instructions of the block are processed in parallel for instruction decode and branch prediction to maintain a high rate of instruction flow through the pipeline.
摘要翻译： 用于预测对计算机流水线的指令高速缓存的下一个指令索引的下一行预测机制具有等于指令高速缓冲存储器的循环时间的等待时间，以使指令高速缓存中的指令带宽最大化。 指令高速缓存输出由行预测机制提供的下一指令索引发起的每次提取的指令块。 块的指令被并行处理，用于指令解码和分支预测，以保持高流量的指令流经管线。
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24.发明授权Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery 失效具有包含顺序列表的寄存器映射系统的寄存器映射系统，用于在精确的分支后恢复中预测循环中的寄存器
公开(公告)号：US5197132A
公开(公告)日：1993-03-23
申请号：US546411
申请日：1990-06-29
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3863
摘要： A register map having a free list of available physical locations in a register file, a log containing a sequential listing of logical registers changed during a predetermined number of cycles, a back-up map associating the logical registers with corresponding physical homes at a back-up point in a computer pipeline operation and a predicted map associating the logical registers with corresponding physical homes at a current point in the computer pipeline operation. A set of valid bits is associated with the maps to indicate whether a particular logical register is to be taken from the back-up map or the predicted map indication of a corresponding physical home. The valid bits can be "flash cleared" in a single cycle to back-up the computer pipeline to the back-up point during a trap event.
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25.发明授权Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline 失效使用环形缓冲器的SUBROUTINE返回预测机制，并与实际地址进行比较以预测地址以验证或冲洗管道
公开(公告)号：US5179673A
公开(公告)日：1993-01-12
申请号：US451943
申请日：1989-12-18
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/4426
摘要： A method and arrangement for producing a predicted subroutine return address in response to entry of a subroutine return instruction in a computer pipeline that has a ring pointer counter and a ring buffer coupled to the ring pointer counter. The ring pointer counter contains a ring pointer that is changed when either a subroutine call instruction or return instruction enters the computer pipeline. The ring buffer has buffer locations which store a value present at its input into the buffer location pointed to by the ring pointer when a subroutine call instruction enters the pipeline. The ring buffer provides a value from the buffer location pointed to by the ring pointer when a subroutine return instruction enters the computer pipeline, this provided value being the predicted subroutine return address.
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26.发明授权Consistency evaluation of program execution across at least one memory barrier 有权至少一个记忆障碍的程序执行的一致性评估公开(公告)号：US08301844B2
公开(公告)日：2012-10-30
申请号：US10756534
申请日：2004-01-13
IPC分类号： G06F13/38
CPC分类号： G06F12/0808
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system including a processor that executes program instructions across at least one memory barrier. A request engine may provide an updated data fill corresponding to an invalid cache line. The invalid cache line may be associated with at least one executed load instruction. A load compare component may compare the invalid cache line to the updated data fill to evaluate the consistency of the at least one executed load instruction.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括跨越至少一个存储器屏障执行程序指令的处理器。 请求引擎可以提供对应于无效高速缓存行的更新的数据填充。 无效高速缓存行可以与至少一个执行的加载指令相关联。 负载比较组件可以将无效高速缓存行与更新的数据填充进行比较，以评估至少一个执行的加载指令的一致性。
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27.发明授权System and method for resolving transactions in a cache coherency protocol 有权用于解决高速缓存一致性协议中的事务的系统和方法公开(公告)号：US08176259B2
公开(公告)日：2012-05-08
申请号：US10760813
申请日：2004-01-20
IPC分类号： G06F13/38
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0828
摘要： A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.
摘要翻译： 系统包括采用源广播协议来发起事务的第一节点。 如果源广播协议不能提供事务的确定性分辨率，则第一节点采用前进进程协议来解决事务。
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28.发明授权Multi-processor systems and methods for backup for non-coherent speculative fills 失效用于非相干投机填充的多处理器系统和备份方法公开(公告)号：US07406565B2
公开(公告)日：2008-07-29
申请号：US10756637
申请日：2004-01-13
CPC分类号： G06F9/383 , G06F9/384 , G06F9/3842 , G06F9/3863 , G06F12/0815
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括具有处理器流水线的处理器，处理器流水线通过响应于源请求而提供的来自推测填充的数据执行程序指令，以及备份系统，其保留与先前处理器执行状态相关联的信息 对应于与投机填充相关联的指令。 如果确定推测填充是非相干的，则备用系统可以启动处理器管线的备份到先前的处理器执行状态，并且如果确定推测填充是相干的，则处理器流水线可以继续执行程序指令。
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29.发明授权System and method for conflict responses in a cache coherency protocol with ordering point migration 有权具有排序点迁移的缓存一致性协议中的冲突响应的系统和方法公开(公告)号：US07395374B2
公开(公告)日：2008-07-01
申请号：US10760651
申请日：2004-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
摘要翻译： 公开了用于不同高速缓存一致性协议之间的交互的系统和方法。 一个系统可以包括家庭节点，其在第一高速缓存一致性协议中从第一节点接收对数据的请求。 第二节点向来自家节点的数据的请求提供冲突响应。 冲突响应指示数据的排序点根据与第一高速缓存一致性协议不同的第二高速缓存一致性协议进行迁移。
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公开(公告)号：US07376794B2
公开(公告)日：2008-05-20
申请号：US10756636
申请日：2004-01-13
CPC分类号： G06F12/0822
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.
摘要翻译： 公开了多处理器系统和方法。 一个实施例可以包括多处理器系统，其包括响应于源处理器的源请求而提供给源处理器的至少一个数据填充，以及由多处理器系统生成的相干信号，其提供哪个数据填充的指示 所述至少一个数据填充是相干数据填充。
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