公开(公告)号：US07974595B2

公开(公告)日：2011-07-05

申请号：US12013221

申请日：2008-01-11

Applicant: Vijay Kumar Reddy ,  Andrew Marshall ,  Siraj Akhtar ,  Srikanth Krishnan ,  Karan Singh Bhatia

Inventor： Vijay Kumar Reddy ,  Andrew Marshall ,  Siraj Akhtar ,  Srikanth Krishnan ,  Karan Singh Bhatia

IPC: H04B17/00 ,  H03C1/62

CPC classification number: G01R31/2879 ,  G01R31/3161

Abstract: One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.

Abstract translation: 一个实施例涉及片上功率放大器（PA）测试电路。 在一个实施例中，PA测试电路包括被配置为产生射频（RF）信号的可控振荡器（CO），调谐到射频的并联谐振电路，耦合到CO的预功率放大器（PPA）和 并联谐振电路，PPA被配置为放大并将RF信号从PPA的输出驱动到负载中。 测试电路还可以包括被配置为将来自CO的RF信号耦合到PPA的输入的第一传输门。 PA测试电路的一种测试方法包括用RF信号强迫PPA，测量PPA的特性，从特征测量确定应力退化，并重复应力和特征测量，直到达到最大应力退化或最大应力 已被应用。

公开(公告)号：US20110124306A1

公开(公告)日：2011-05-26

申请号：US13008489

申请日：2011-01-18

Applicant: Petteri Matti Litmanen ,  Siraj Akhtar

Inventor： Petteri Matti Litmanen ,  Siraj Akhtar

IPC: H04B1/04

CPC classification number: H03F3/245 ,  H03F3/195 ,  H03F3/45179 ,  H03F2200/18 ,  H03F2200/336 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2200/72 ,  H03F2203/45154 ,  H03F2203/45304 ,  H03F2203/45311 ,  H03G1/0029 ,  H03G7/001 ,  H04L27/362

Abstract: A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON transistor, a first control transistor and a first subtracting transistor. The second leg has a second input line, a second output line, a second ON transistor, a second control transistor and a second subtracting transistor. The second input line can provide a second input current. The second output line can provide a second output current. The first input line is arranged to provide a first input current to each of the first ON transistor, the first control transistor and the first subtracting transistor. The second input line is arranged to provide a second input current to each of the second ON transistor, the second control transistor and the second subtracting transistor. The first output line is in electrical connection with each of the first ON transistor, the first control transistor and the second subtracting transistor. The second output line is in electrical connection with each of the second ON transistor, the second control transistor and the first subtracting transistor.

Abstract translation: 电流消除CMOS可变增益放大器包括第一支路和第二支路。 第一支路具有第一输入线，第一输出线，第一ON晶体管，第一控制晶体管和第一减法晶体管。 第二支路具有第二输入线，第二输出线，第二ON晶体管，第二控制晶体管和第二减法晶体管。 第二输入线可以提供第二输入电流。 第二输出线可以提供第二输出电流。 第一输入线被布置成向第一ON晶体管，第一控制晶体管和第一减法晶体管中的每一个提供第一输入电流。 第二输入线被布置成向第二ON晶体管，第二控制晶体管和第二减法晶体管中的每一个提供第二输入电流。 第一输出线与第一ON晶体管，第一控制晶体管和第二减法晶体管中的每一个电连接。 第二输出线与第二ON晶体管，第二控制晶体管和第一减法晶体管中的每一个电连接。

公开(公告)号：US07936229B2

公开(公告)日：2011-05-03

申请号：US11852939

申请日：2007-09-10

Applicant: Siraj Akhtar ,  Mehmet Ipek ,  Robert B. Staszewski

Inventor： Siraj Akhtar ,  Mehmet Ipek ,  Robert B. Staszewski

IPC: H03B27/00 ,  H03C1/00 ,  H03C3/00 ,  H03L7/00

CPC classification number: H04L27/361 ,  H03B19/14 ,  H03C5/00 ,  H04B1/0483

Abstract: A novel and useful apparatus for and method of local oscillator generation employing an exception handling mechanism that permits an oscillator having a limited modulation range to handle the large modulation ranges demanded by modern wideband wireless standards such as 3G WCDMA, etc. A controllable oscillator generates an RF signal having four quadrature phases in accordance with an input command signal. An exception handler compares the frequency command information against a threshold. If it exceeds the threshold a phase jump and a residue frequency command are generated. The residue frequency command is input to an oscillator which is operative to generate an RF signal having four quadrature phases. The phase jump is input to a quadrature switch which functions to select one of the four quadrature phase signals as the output RF signal which is then fed to a digital power amplifier.

Abstract translation: 一种新颖有用的本地振荡器生成方法和采用异常处理机制的方法，其允许具有有限调制范围的振荡器来处理诸如3G WCDMA等现代宽带无线标准所要求的大调制范围。可控振荡器产生 RF信号根据输入命令信号具有四个正交相位。 异常处理程序将频率命令信息与阈值进行比较。 如果超过阈值，则产生相位跳变和残留频率指令。 剩余频率指令被输入到可产生具有四个正交相位的RF信号的振荡器。 相位跳变被输入到正交开关，其用于选择四个正交相位信号中的一个作为输出RF信号，然后馈送到数字功率放大器。

公开(公告)号：US20070188243A1

公开(公告)日：2007-08-16

申请号：US11618034

申请日：2006-12-29

Applicant: Khurram Waheed ,  Siraj Akhtar ,  Robert B. Staszewski

Inventor： Khurram Waheed ,  Siraj Akhtar ,  Robert B. Staszewski

IPC: H03L7/00

CPC classification number: H03L7/099 ,  H03C5/00 ,  H03L7/10 ,  H03L2207/50

Abstract: A novel apparatus and method of extending the frequency tuning range and improving the modulation resolution of an RF digitally controlled oscillator (DCO). In addition to the coarse PVT MIM varactor bank, the DCO uses a single unified bank of varactors that is further subdivided divided into an MSB bank, LSB bank and sigma-delta (SD-LSB) bank. Any ratio mismatches between MSBs and LSBs are digitally calibrated out using a DCO step-size pre-distortion scheme wherein the LSB steps are adjusted to account for the ratio mismatch between the MSB/LSB step sizes. A harmonic characterization technique is used to estimate the mismatches in the minimal size CMOS tuning varactors of a digitally controlled RF oscillator (DCO), wherein the nominal ratio mismatch between the MSB and LSB devices is estimated using hybrid stochastic gradient DCO gain estimation algorithms. The nominal ratio mismatch and the mismatches in the MSB and LSB banks are used to determine the average MSB/LSB mismatch. The average mismatch value is then used to correct the LSB steps.

Abstract translation: 一种扩展频率调谐范围并提高RF数字控制振荡器（DCO）的调制分辨率的新型装置和方法。 除了粗略的PVT MIM变容二极管组外，DCO还使用单个统一的变容二极管组，进一步细分为MSB组，LSB组和Σ-Δ（SD-LSB）组。 使用DCO步长预失真方案对MSB和LSB之间的任何比例不匹配进行数字校准，其中LSB步长被调整以考虑MSB / LSB步长之间的比率失配。 使用谐波表征技术来估计数字控制RF振荡器（DCO）的最小尺寸CMOS调谐变容二极管中的不匹配，其中使用混合随机梯度DCO增益估计算法来估计MSB和LSB器件之间的标称比率失配。 标称比例失配和MSB和LSB组中的不匹配用于确定平均MSB / LSB失配。 然后使用平均不匹配值来校正LSB步长。