公开(公告)号：US20190393206A1

公开(公告)日：2019-12-26

申请号：US16438026

申请日：2019-06-11

Applicant: SOCIONEXT INC.

Inventor： Wenzhen WANG ,  Hirotaka TAKENO ,  Atsushi OKAMOTO

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

公开(公告)号：US20250056879A1

公开(公告)日：2025-02-13

申请号：US18929016

申请日：2024-10-28

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

公开(公告)号：US20230223381A1

公开(公告)日：2023-07-13

申请号：US18179013

申请日：2023-03-06

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/50 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US20220231053A1

公开(公告)日：2022-07-21

申请号：US17577994

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Hirotaka TAKENO ,  Atsushi OKAMOTO ,  Toshio HINO

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

公开(公告)号：US20190123741A1

公开(公告)日：2019-04-25

申请号：US16206874

申请日：2018-11-30

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Tomoyasu KITAURA ,  Hirotaka TAKENO

IPC: H03K17/687 ,  H01L27/02

Abstract: Power switch cells (20) respectively includes power switches (21), each of which is capable of performing switching between electrical connection and disconnection between a global power supply line (11) and a local power supply line (8) in accordance with a control signal (CTR). The power switches (21) are connected in a chain state to constitute a chain connection through which the control signal (CTR) is sequentially transmitted. A starting point switch (21a) in the chain connection has a greater distance to an edge (BE) of a region occupied by a power domain than an ending point switch (21b).