公开(公告)号：US11876020B2

公开(公告)日：2024-01-16

申请号：US17250767

申请日：2019-09-03

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US11127775B2

公开(公告)日：2021-09-21

申请号：US16477374

申请日：2018-01-10

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L27/12

Abstract: A substrate for a front-side-type image sensor includes, successively, a supporting semiconductor substrate, an electrically insulating layer, and a semiconductor layer, known as the active layer. The active layer is an epitaxial layer of silicon-germanium having a germanium content of less than 10%. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US11114314B2

公开(公告)日：2021-09-07

申请号：US16305695

申请日：2017-05-24

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Ludovic Ecarnot ,  Nadia Ben Mohamed ,  Christophe Malville

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

公开(公告)号：US20210202326A1

公开(公告)日：2021-07-01

申请号：US17250767

申请日：2019-09-03

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/324

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type, comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US20200295138A1

公开(公告)日：2020-09-17

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US10777447B2

公开(公告)日：2020-09-15

申请号：US16081816

申请日：2017-03-02

Applicant: Soitec

Inventor： Ludovic Ecarnot ,  Nadia Ben Mohammed ,  Carine Duret

IPC: H01L21/762 ,  H01L21/66 ,  H01L21/02 ,  H01L21/20 ,  H01L21/84

Abstract: A method for determining a suitable implanting energy of at least two atomic species in a donor substrate to create a weakened zone defining a monocrystalline semiconductor layer to be transferred onto a receiver substrate, comprises the following steps:(i) forming a dielectric layer on at least one of the donor substrate and the receiver substrate;(ii) co-implanting the species in the donor substrate;(iii) bonding the donor substrate on the receiver substrate;(iv) detaching the donor substrate along the weakened zone to transfer the monocrystalline semiconductor layer and recover the remainder of the donor substrate;(v) inspecting the peripheral crown of the remainder of the donor substrate, or of the receiver substrate on which the monocrystalline semiconductor layer was transferred at step (iv);(vi) if the crown exhibits zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is too high;(vii) if said the crown does not exhibit zones transferred onto the receiver substrate, determining the fact that the implanting energy at step (ii) is suitable.

公开(公告)号：US10703627B2

公开(公告)日：2020-07-07

申请号：US15328371

申请日：2014-06-11

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ludovic Ecarnot

IPC: B81C1/00 ,  B81B1/00

Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

公开(公告)号：US20250072111A1

公开(公告)日：2025-02-27

申请号：US18937744

申请日：2024-11-05

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Manuel Sellier ,  Ludovic Ecarnot

IPC: H01L27/12 ,  H01L27/146

Abstract: The invention relates to a front-side imager comprising in succession: a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises, between the carrier substrate and the first electrically insulating layer: a second electrically insulating separating layer, and a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.

公开(公告)号：US12198975B2

公开(公告)日：2025-01-14

申请号：US17444230

申请日：2021-08-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/146 ,  H01L31/028

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

公开(公告)号：US12148755B2

公开(公告)日：2024-11-19

申请号：US17254808

申请日：2019-06-21

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Manuel Sellier ,  Ludovic Ecarnot

IPC: H01L27/12 ,  H01L27/146

Abstract: The invention relates to a front-side imager comprising in succession: —a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises between the carrier substrate and the first electrically insulating layer: —a second electrically insulating separating layer, and —a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.