公开(公告)号：US11205702B2

公开(公告)日：2021-12-21

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00 ,  H01L21/306

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US11127624B2

公开(公告)日：2021-09-21

申请号：US16495362

申请日：2018-03-21

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L27/146 ,  H01L31/028 ,  H01L21/02 ,  H01L21/203

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

公开(公告)号：US20200328094A1

公开(公告)日：2020-10-15

申请号：US16305695

申请日：2017-05-24

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Ludovic Ecarnot ,  Nadia Ben Mohamed ,  Christophe Malville

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

公开(公告)号：US10163682B2

公开(公告)日：2018-12-25

申请号：US15603830

申请日：2017-05-24

Applicant: Soitec

Inventor： Cédric Malaquin ,  Ludovic Ecarnot ,  Damien Parissi

IPC: H01L21/762 ,  H01L21/322 ,  H01L21/365 ,  H01L21/265 ,  H01L21/18

Abstract: The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.

公开(公告)号：US20170345709A1

公开(公告)日：2017-11-30

申请号：US15603830

申请日：2017-05-24

Applicant: Soitec

Inventor： Cédric Malaquin ,  Ludovic Ecarnot ,  Damien Parissi

IPC: H01L21/762

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/26506 ,  H01L21/3226 ,  H01L21/76251

Abstract: The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer.

公开(公告)号：US20220319910A1

公开(公告)日：2022-10-06

申请号：US17597583

申请日：2020-07-13

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  Soitec

Inventor： Vincent Larrey ,  François Rieutord ,  Jean-Michel Hartmann ,  Frank Fournel ,  Didier Landru ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L21/02

Abstract: A process for hydrophilic bonding first and second substrates, comprising: —bringing the first and second substrates into contact to form a bonding interface between main surfaces of the first and second substrates, and —applying a heat treatment to close the bonding interface. The process further comprises, before the step of bringing into contact, depositing, on the main surface of the first and/or second substrate, a bonding layer comprising a non-metallic material that is permeable to dihydrogen and that has, at the temperature of the heat treatment, a yield strength lower than that of at least one of the materials of the first substrate and of the second substrate located at the bonding interface. The layer has a thickness between 1 and 6 nm, and the heat treatment is carried out at a temperature lower than or equal to 900° C., and preferably lower than or equal to 600° C.

公开(公告)号：US20220157882A1

公开(公告)日：2022-05-19

申请号：US17649982

申请日：2022-02-04

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L21/762

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US11282889B2

公开(公告)日：2022-03-22

申请号：US16477499

申请日：2018-01-10

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L21/762

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US20210366763A1

公开(公告)日：2021-11-25

申请号：US17444230

申请日：2021-08-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L27/146 ,  H01L31/028 ,  H01L21/02 ,  H01L21/203

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

公开(公告)号：US20200331750A1

公开(公告)日：2020-10-22

申请号：US16921675

申请日：2020-07-06

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ludovic Ecarnot

IPC: B81C1/00 ,  B81B1/00

Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.