公开(公告)号：US20190065658A1

公开(公告)日：2019-02-28

申请号：US15966693

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei PENG ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Shun Li Chen ,  Wei-Cheng Lin

IPC: G06F17/50 ,  H01L27/02

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on the first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on a first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule.

公开(公告)号：US20180337167A1

公开(公告)日：2018-11-22

申请号：US16051241

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L29/423 ,  G06F17/50 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L27/092 ,  H01L29/42376 ,  H01L2027/11875

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US10127340B2

公开(公告)日：2018-11-13

申请号：US15370418

申请日：2016-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mao-Wei Chiu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Chi-Yu Lu

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/528

Abstract: A method of designing, for a semiconductor device, a layout which includes standard spare cells. Such a method includes: generating a set of possible values for a first pitch of standard spare cells based on a second pitch of strap lines of a metallization layer; selecting one member of the possible values set to be the first pitch; and placing standard spare cells into a logic area of the layout according to the first pitch; wherein at least one of the generating, selecting and placing is executed by a processor of a computer.

公开(公告)号：US09899263B2

公开(公告)日：2018-02-20

申请号：US15150149

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Min-Hsiung Chiang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/304 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/118

CPC classification number: H01L21/82345 ,  G06F17/5072 ,  H01L21/3043 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

公开(公告)号：US09831230B2

公开(公告)日：2017-11-28

申请号：US13965648

申请日：2013-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Li-Chun Tien ,  Ya-Chi Chou ,  Hui-Zhong Zhuang ,  Chun-Fu Chen ,  Ting-Wei Chiang ,  Hsiang Jen Tseng

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

公开(公告)号：US09501600B2

公开(公告)日：2016-11-22

申请号：US14051881

申请日：2013-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shang-Chih Hsieh ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng

IPC: G06F17/50 ,  H03K19/02 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L27/0207 ,  H03K19/02

Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.

Abstract translation: 通过具有金属线的标称最小间距的预定制造工艺制造集成电路。 集成电路包括沿着第一方向延伸的多条金属线和多条金属线下的多个标准单元。 多个金属线在与第一方向垂直的第二方向上以标称最小间距的整数倍分开。 多个标准单元包括被配置为执行预定功能并具有第一布局的第一标准单元和被配置为执行预定功能并且具有与第一布局不同的第二布局的第二标准单元。 第一和第二标准单元沿着第二方向具有单元高度（H），单元高度是标称最小间距的非整数倍。

公开(公告)号：US09412700B2

公开(公告)日：2016-08-09

申请号：US14515276

申请日：2014-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Wang ,  Li-Chun Tien

IPC: H01L27/088 ,  H01L23/535 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L29/401 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

Abstract translation: 半导体器件包括具有有源区的衬底，衬底顶表面上的第一栅极结构，衬底顶表面上的第二栅极结构，第一栅极结构的每个侧壁上的一对第一间隔物， 在所述第二栅极结构的每个侧壁上的一对第二间隔物，至少所述第一栅极结构上的绝缘层，所述有源区上的第一导电特征和所述衬底上的第二导电特征。 此外，第二栅极结构与第一栅极结构相邻，并且第一导电特征的顶表面与第二导电特征的顶表面共面。

公开(公告)号：US09158877B2

公开(公告)日：2015-10-13

申请号：US14015924

申请日：2013-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shang-Chih Hsieh ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng

IPC: G06F17/50 ,  H01L29/78

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/785

Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.

Abstract translation: 半导体结构包括第一有源区结构，围绕第一有源区结构的隔离结构，第一多晶硅结构，第一金属结构和第二金属结构。 第一个多晶硅结构超过了第一个有源区结构。 第一金属结构直接在第一有源区结构的第一部分之上。 第二金属结构直接与第一多晶硅结构的一部分接触并与第一金属结构接触。

公开(公告)号：US12243914B2

公开(公告)日：2025-03-04

申请号：US17815087

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L29/06 ,  G06F30/392 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.

公开(公告)号：US12224285B2

公开(公告)日：2025-02-11

申请号：US17828981

申请日：2022-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-Wei Hsu ,  Shun Li Chen ,  Ting Yu Chen ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L27/118

Abstract: An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.