公开(公告)号：US20190181842A1

公开(公告)日：2019-06-13

申请号：US15839265

申请日：2017-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sundarrajan RANGACHARI ,  Jaiganesh BALAKRISHNAN ,  Jawaharlal TANGUDU ,  Srinivas Kumar Reddy NARU

IPC: H03H17/02

Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

公开(公告)号：US20180097525A1

公开(公告)日：2018-04-05

申请号：US15674175

申请日：2017-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Chandrasekhar SRIRAM

IPC: H03M1/08

CPC classification number: H03M1/08 ,  H03M1/06 ,  H03M1/0836 ,  H03M1/0854 ,  H03M1/1042

Abstract: Circuitry for correcting non-linearity of an analog-to-digital converter. A non-linearity correction system for an analog-to-digital converter (ADC) includes coefficient storage, coefficient transformation circuitry, and correction circuitry. The coefficient storage is encoded with a first set of coefficients for correcting non-linearity of the ADC at a first sampling rate. The coefficient transformation circuitry is coupled to the coefficient storage. The coefficient transformation circuitry is configured to generate a second set of coefficients for correcting non-linearity of the ADC at a different sampling rate. The correction circuitry is configured to apply the second set of coefficients to correct non-linearity in output of the ADC while the ADC is operating at the different sampling rate.

公开(公告)号：US20170322773A1

公开(公告)日：2017-11-09

申请号：US15587096

申请日：2017-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Suvam NANDI ,  Pooja SUNDAR ,  Jaiganesh BALAKRISHNAN

IPC: G06F7/523 ,  H03D7/16 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50 ,  H03D7/161

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

公开(公告)号：US20170070952A1

公开(公告)日：2017-03-09

申请号：US15259703

申请日：2016-09-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh BALAKRISHNAN ,  Jawaharlal TANGUDU ,  Sreenath Potty NARAYANAN

IPC: H04W52/02 ,  H04W24/08 ,  H04L12/26

CPC classification number: H04W52/0203 ,  Y02D70/00

Abstract: A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.

Abstract translation: 重采样器包括被配置为接收输入采样的第一CSD乘法器，耦合到第一CSD乘法器并被配置为与第一CSD乘法器形成第一MAC单元的第一累加器，被配置为接收输入采样的第二CSD乘法器，以及 耦合到所述第二CSD乘法器并被配置为与所述第二CSD乘法器形成第二MAC单元的第二累加器，其中所述重新采样器被配置为基于所述输入采样来生成输出采样。 一种方法包括由第一CSD乘法器接收输入采样，由第二CSD乘法器接收输入采样，使用第一CSD乘法器和第二CSD乘法器生成系数，缩放，具有与 所述系数用于形成系数矢量缩放输入样本，并且基于系数向量缩放输入样本生成输出样本。 CSD乘法器可以是MC-CSD乘法器。