公开(公告)号：US20230155628A1

公开(公告)日：2023-05-18

申请号：US18100131

申请日：2023-01-23

Applicant: Texas Instruments Incorporated

Inventor： Srijan Rastogi ,  Mayank Garg ,  Anant Shankar Kamath

IPC: H04B3/36 ,  H03F3/45

CPC classification number: H04B3/36 ,  H03F3/45179

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

公开(公告)号：US11309892B2

公开(公告)日：2022-04-19

申请号：US17174119

申请日：2021-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H04B3/36 ,  G06F13/42 ,  H04L25/02 ,  H03K19/0185 ,  H04L7/00

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US20210294302A1

公开(公告)日：2021-09-23

申请号：US17339213

申请日：2021-06-04

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Mayank Garg

IPC: G05B19/414

Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.

公开(公告)号：US20210157299A1

公开(公告)日：2021-05-27

申请号：US16692674

申请日：2019-11-22

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Mayank Garg

IPC: G05B19/414

Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.

公开(公告)号：US20210044294A1

公开(公告)日：2021-02-11

申请号：US17082937

申请日：2020-10-28

Applicant: Texas Instruments Incorporated

Inventor： Mayank Garg ,  Shu-Ing Ju ,  Arun Rao ,  Wei Zhang

IPC: H03K17/687 ,  H03K17/693

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

公开(公告)号：US11984941B2

公开(公告)日：2024-05-14

申请号：US18100131

申请日：2023-01-23

Applicant: Texas Instruments Incorporated

Inventor： Srijan Rastogi ,  Mayank Garg ,  Anant Shankar Kamath

IPC: H04B3/36 ,  H03F3/45

CPC classification number: H04B3/36 ,  H03F3/45179

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

公开(公告)号：US11556492B1

公开(公告)日：2023-01-17

申请号：US17363106

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Ganapathi Hegde ,  Krushal Shah ,  Mayank Garg ,  Luis Eduardo Ossa ,  Vashist Bist

IPC: G06F13/42

Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

公开(公告)号：US20220224335A1

公开(公告)日：2022-07-14

申请号：US17700045

申请日：2022-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  H04L7/00 ,  H04B3/36 ,  G06F13/42 ,  H04L25/02

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US20200328715A1

公开(公告)日：2020-10-15

申请号：US16843962

申请日：2020-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luis Eduardo Ossa ,  Krushal Shah ,  Mayank Garg ,  Hao Wang ,  Haozhi Liu

IPC: H02P27/08 ,  H02P1/26 ,  H02P25/03

Abstract: A system for driving one or more motors includes: a controller having an instruction output; one or more motor drivers, each of the motor drivers are coupled to the instruction output of the controller and each of the motor drivers having a unique address; and wherein each motor driver is only operable to receive instruction from the controller when its unique address is provided by the controller at the instruction output.

公开(公告)号：US10700586B2

公开(公告)日：2020-06-30

申请号：US15142852

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shyamsunder Balasubramanian ,  Toshio Yamanaka ,  Toru Tanaka ,  Mayank Garg

IPC: H02P29/02 ,  H02P6/08 ,  H03K5/134 ,  H02P6/12 ,  H02M1/08 ,  H02M1/32 ,  H03K17/12 ,  H02P29/024 ,  H03K17/0812 ,  H03K17/687

Abstract: A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.