公开(公告)号：US11630797B2

公开(公告)日：2023-04-18

申请号：US17341089

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Rakesh Hariharan ,  Vivekkumar Ramanlal Vadodariya ,  Soumi Paul ,  Mayank Garg

IPC: G06F13/42 ,  G06F1/3215 ,  G06F13/38

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

公开(公告)号：US20210250026A1

公开(公告)日：2021-08-12

申请号：US17174119

申请日：2021-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  H04L7/00

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US20220224335A1

公开(公告)日：2022-07-14

申请号：US17700045

申请日：2022-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  H04L7/00 ,  H04B3/36 ,  G06F13/42 ,  H04L25/02

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US20240396554A1

公开(公告)日：2024-11-28

申请号：US18792708

申请日：2024-08-02

Applicant: Texas Instruments Incorporated

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  G06F13/42 ,  H04B3/36 ,  H04L7/00 ,  H04L25/02

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US12088293B2

公开(公告)日：2024-09-10

申请号：US17700045

申请日：2022-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H03K19/0185 ,  G06F13/42 ,  H04B3/36 ,  H04L7/00 ,  H04L25/02

CPC classification number: H03K19/018521 ,  G06F13/4282 ,  H04B3/36 ,  H04L7/0041 ,  H04L25/0272

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

公开(公告)号：US11309892B2

公开(公告)日：2022-04-19

申请号：US17174119

申请日：2021-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bharath Kumar Singareddy ,  Soumi Paul ,  Mayank Garg ,  Suzanne Mary Vining

IPC: H04B3/36 ,  G06F13/42 ,  H04L25/02 ,  H03K19/0185 ,  H04L7/00

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.