公开(公告)号：US20230163772A1

公开(公告)日：2023-05-25

申请号：US18159305

申请日：2023-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

公开(公告)号：US11592484B2

公开(公告)日：2023-02-28

申请号：US17165326

申请日：2021-02-02

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

IPC: G01R31/3185 ,  G06F21/45 ,  G06F21/31 ,  H04L9/40

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

公开(公告)号：US11570468B2

公开(公告)日：2023-01-31

申请号：US17520795

申请日：2021-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aishwarya Dubey ,  Shashank Dabral ,  Veeramanikandan Raju

IPC: H04N19/557 ,  H04N19/577 ,  H04N19/567 ,  G01S17/89 ,  G01S17/86

Abstract: Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.

公开(公告)号：US11172219B2

公开(公告)日：2021-11-09

申请号：US16866647

申请日：2020-05-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aishwarya Dubey ,  Shashank Dabral ,  Veeramanikandan Raju

IPC: H04N19/557 ,  H04N19/577 ,  G01S17/89 ,  G01S17/86 ,  H04N19/567

Abstract: Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.

公开(公告)号：US20210156919A1

公开(公告)日：2021-05-27

申请号：US17165326

申请日：2021-02-02

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

IPC: G01R31/3185 ,  G06F21/45 ,  G06F21/31 ,  H04L29/06

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

公开(公告)号：US09918067B2

公开(公告)日：2018-03-13

申请号：US15226430

申请日：2016-08-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Gregory R. Hewes

IPC: G06T15/00 ,  H04N13/00

CPC classification number: H04N13/133 ,  H04N13/128 ,  H04N13/144

Abstract: The present invention is drawn to a device for use with first stereoscopic data, second stereoscopic data and a display device. The device includes an input portion, a convergence data detecting portion, a convergence plane portion, a comparing portion and a modification portion. The input portion can receive the first stereoscopic data and the second stereoscopic data. The convergence data detecting portion can detect first convergence data within the first stereoscopic data and can detect second convergence data within the second stereoscopic data. The convergence plane portion can determine a first convergence plane based on the first convergence data and can determine a second convergence plane based on the second convergence data. The comparing portion can compare the first convergence plane and the second convergence plane and can generate a convergence plane comparison. The modification portion can modify the first convergence data based on the convergence plane comparison.

公开(公告)号：US09569447B2

公开(公告)日：2017-02-14

申请号：US14075757

申请日：2013-11-08

Applicant: Texas Instruments Incorporated

Inventor： Madan Srinivas ,  Veeramanikandan Raju ,  Keshava Munegowda

IPC: G06F17/30

CPC classification number: G06F17/30109 ,  G06F17/30091 ,  G06F17/30094 ,  G06F17/30203

Abstract: Several systems and methods for accessing files stored in a storage device are disclosed. In an embodiment, the method includes accessing a file allocation table (FAT) in a computer file system associated with the storage device. The FAT includes a plurality of cluster addresses corresponding to a plurality of clusters allocated to a file stored in the storage device. A cluster address is read to identify a location of a next cluster. One or more bits in the cluster address are read to determine a presence of a signature value indicating allocation of a set of contiguous clusters from among the plurality of clusters. A number of contiguous clusters is computed based on a pre-determined number of consecutive cluster addresses succeeding the cluster address if the signature value is present. The set of contiguous clusters are read from the storage device based on the computed number of contiguous clusters.

Abstract translation: 公开了用于访问存储在存储设备中的文件的几种系统和方法。 在一个实施例中，该方法包括访问与存储设备相关联的计算机文件系统中的文件分配表（FAT）。 FAT包括与分配给存储在存储装置中的文件的多个集群相对应的多个集群地址。 读取集群地址以标识下一个集群的位置。 读取集群地址中的一个或多个位以确定表示从多个集群中分配一组连续集群的签名值的存在。 如果签名值存在，则基于簇聚合地址后续的连续簇地址的预定数量来计算多个连续簇。 基于所计算的连续簇的数量，从存储设备读取连续簇的集合。

公开(公告)号：US20250138825A1

公开(公告)日：2025-05-01

申请号：US18498423

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Mihir Mody ,  Shailesh Ghotgalkar

IPC: G06F9/30 ,  G06F11/07

Abstract: A system for prefetching program code from flash memory that includes processing circuitry configured to execute program code and prefetch circuitry coupled to the processing circuitry. In an implementation, the prefetch circuitry is configured to analyze branch logic within the program code to identify a block of code to prefetch from flash memory. Once identified, the prefetch circuitry causes the block of code to be prefetched from flash memory and loaded to a memory buffer. In another implementation, the prefetch circuitry is further configured to receive a request to supply the processing circuitry with the block of code. Upon receiving the request, the prefetch circuitry determines that the block of code has already been fetched and loaded in the memory buffer. Once identified in the memory buffer, the prefetch circuitry causes the block of code to be supplied to the processing circuitry.

公开(公告)号：US20240183885A1

公开(公告)日：2024-06-06

申请号：US18438754

申请日：2024-02-12

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Aravindhan Karuppiah

IPC: G01R19/10 ,  G01R19/165 ,  G01R19/25

CPC classification number: G01R19/10 ,  G01R19/16576 ,  G01R19/2506

Abstract: An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.

公开(公告)号：US11933823B1

公开(公告)日：2024-03-19

申请号：US17962139

申请日：2022-10-07

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Aravindhan Karuppiah

IPC: G01R19/10 ,  G01R19/165 ,  G01R19/25

CPC classification number: G01R19/10 ,  G01R19/16576 ,  G01R19/2506

Abstract: An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.