公开(公告)号：US11601065B1

公开(公告)日：2023-03-07

申请号：US17461423

申请日：2021-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Makoto Shibuya ,  Kengo Aoya

IPC: H02M3/00 ,  H02M7/00 ,  H02M7/527 ,  H01L29/16 ,  H01L29/20 ,  H02M3/158

Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.

公开(公告)号：US20230015323A1

公开(公告)日：2023-01-19

申请号：US17379934

申请日：2021-07-19

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.

公开(公告)号：US11387179B2

公开(公告)日：2022-07-12

申请号：US16827455

申请日：2020-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Kengo Aoya ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/64 ,  H01L49/02 ,  H01L23/00 ,  H01L21/8234 ,  H01L21/48

Abstract: An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.

公开(公告)号：US11302615B2

公开(公告)日：2022-04-12

申请号：US16840407

申请日：2020-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

公开(公告)号：US20210111105A1

公开(公告)日：2021-04-15

申请号：US16597808

申请日：2019-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H02M3/156 ,  H01L25/065

Abstract: A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.

公开(公告)号：US20200091048A1

公开(公告)日：2020-03-19

申请号：US16134924

申请日：2018-09-18

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L23/532 ,  H01L21/48

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US20190287918A1

公开(公告)日：2019-09-19

申请号：US15920242

申请日：2018-03-13

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/552 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: Integrated circuit (IC) packages with shields and methods of producing the same are disclosed. A disclosed IC package includes a lead frame including a die attach pad and a plurality of leads, a die attached to the die attach pad and electrically coupled to the plurality of leads, package encapsulate covering portions of the lead frame and the die, where the package encapsulate includes an indentation at a periphery of the IC package, and where the indentation includes sidewalls. The example IC package also includes a shield in the indentation, where a surface of the shield is coplanar with a surface of the package encapsulate.

公开(公告)号：US20250087591A1

公开(公告)日：2025-03-13

申请号：US18960733

申请日：2024-11-26

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US12125799B2

公开(公告)日：2024-10-22

申请号：US17517608

申请日：2021-11-02

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3735 ,  H01L23/49861

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

公开(公告)号：US20230386963A1

公开(公告)日：2023-11-30

申请号：US17828803

申请日：2022-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： WOOCHAN KIM ,  Vivek Kishorechand Arora ,  Ninad Shahane ,  Makoto Shibuya

IPC: H01L23/373 ,  H01L23/66 ,  H01L23/12 ,  H01L23/498 ,  H02M3/155 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/3735 ,  H01L23/66 ,  H01L23/12 ,  H01L23/49811 ,  H02M3/155 ,  H01L25/18 ,  H01L24/48 ,  H01L2924/1033 ,  H01L2224/05567

Abstract: A power converter module includes a substrate having a first surface and a second surface that opposes the first surface. The power converter module includes a thick printed copper (TPC) substrate on the first surface of the substrate. The TPC substrate includes a first layer having TPC patterned on the first surface of the substrate and a second layer with dielectric patterned on the first layer. The TPC substrate includes a third layer having TPC patterned on the second layer. The power converter module includes power transistors mounted on the TPC substrate and a control integrated circuit (IC) chip mounted on the TPC substrate.