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1.
公开(公告)号:US20230207420A1
公开(公告)日:2023-06-29
申请号:US17563789
申请日:2021-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Kwang-Soo Kim , Vivek Kishorechand Arora , Woochan Kim
IPC: H01L23/373 , H01L29/20 , H01L29/772
CPC classification number: H01L23/3738 , H01L23/3731 , H01L29/2003 , H01L29/772
Abstract: An electronic device for use in power related applications includes a multi-layered substrate comprised of a first metal layer, a second metal layer, and an intermediate layer disposed between the first metal layer, and the second metal layer. The first metal layer is partitioned into sections, where each of the sections has a first surface and electrical circuits patterned onto the first surface. A lead frame is attached to outer portions of the first metal layer and a die is attached to the first surface of each of the sections of the first metal layer.
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公开(公告)号:US20220238424A1
公开(公告)日:2022-07-28
申请号:US17719246
申请日:2022-04-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Anindya Poddar , Woochan Kim , Vivek Kishorechand Arora
IPC: H01L23/498 , H01L23/367 , H01L23/31 , H01L21/48 , H01L23/00 , H01L25/16
Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.
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公开(公告)号:US11183460B2
公开(公告)日:2021-11-23
申请号:US16132906
申请日:2018-09-17
Applicant: Texas Instruments Incorporated
Inventor: Woochan Kim , Mutsumi Masumoto , Kengo Aoya , Vivek Kishorechand Arora , Anindya Poddar
IPC: H01L23/538 , H01L23/373 , H01L21/56 , H01L23/498
Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
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公开(公告)号:US20200161225A1
公开(公告)日:2020-05-21
申请号:US16751088
申请日:2020-01-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Anindya Poddar , Thomas Dyer Bonifield , Woochan Kim , Vivek Kishorechand Arora
IPC: H01L23/495 , H01L21/48 , H01L23/532
Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.
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公开(公告)号:US20250022782A1
公开(公告)日:2025-01-16
申请号:US18901148
申请日:2024-09-30
Applicant: Texas Instruments Incorporated
Inventor: Woochan Kim , Vivek Kishorechand Arora
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/482
Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.
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公开(公告)号:US12154861B2
公开(公告)日:2024-11-26
申请号:US16669666
申请日:2019-10-31
Applicant: Texas Instruments Incorporated
Inventor: Woochan Kim , Masamitsu Matasuura , Mutsumi Masumoto , Kengo Aoya , Hau Thanh Nguyen , Vivek Kishorechand Arora , Anindya Poddar , Hideaki Matsunaga
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31
Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.
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公开(公告)号:US11869839B2
公开(公告)日:2024-01-09
申请号:US17317873
申请日:2021-05-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Woochan Kim , Benjamin Allen Samples , Vivek Kishorechand Arora
IPC: H01L23/522 , H01L23/538 , H01L23/532 , H01L25/07 , H01L49/02 , H01L23/00 , H01L25/00
CPC classification number: H01L23/5226 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L23/53228 , H01L24/09 , H01L25/072 , H01L25/50 , H01L28/40 , H01L2224/0231 , H01L2224/02373 , H01L2224/02381
Abstract: A packaged electronic device includes a semiconductor die with an electronic component and a contact structure connected to the electronic component, as well as an organic panel frame, a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame, and a ceramic substrate mounted to a first side of the semiconductor die.
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8.
公开(公告)号:US20230395514A1
公开(公告)日:2023-12-07
申请号:US17830291
申请日:2022-06-01
Applicant: Texas Instruments Incorporated
Inventor: Kwnag-Soo Kim , Vivek Kishorechand Arora , Woochan Kim
IPC: H01L23/538 , H01L21/48 , H01L23/373
CPC classification number: H01L23/5383 , H01L21/4857 , H01L23/3735 , H01L21/481 , H01L23/3121
Abstract: An example semiconductor package comprises a multi-layer substrate having a bottom metal layer, a top metal layer, and a first insulation layer between bottom metal layer and the top metal layer. A plurality of first conductive traces are formed in the top metal layer. A second insulation layer is disposed over the exposed portions of the first insulation layer and over segments of the first conductive traces. A plurality of second conductive traces formed on top of the second insulation layer. One or more semiconductor dies are mounted on the one or more second segments of the conductive traces. One or more bond wires couple the semiconductor dies to one or more of the second conductive traces. A mold compound covers at least a portion of the semiconductor dies, the second insulation layer, the first conductive traces, and the second conductive traces.
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公开(公告)号:US11158595B2
公开(公告)日:2021-10-26
申请号:US16028741
申请日:2018-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Woochan Kim , Masamitsu Matsuura , Mutsumi Masumoto , Kengo Aoya , Hau Thanh Nguyen , Vivek Kishorechand Arora , Anindya Poddar
IPC: H01L23/48 , H01L23/00 , H01L25/065 , H01L23/532 , H01L21/56 , H01L23/31 , H01L25/00 , H01L23/29 , H01L23/528 , H01L23/522 , H01L23/538 , H01L23/433 , H01L23/367
Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.
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公开(公告)号:US11031332B2
公开(公告)日:2021-06-08
申请号:US16263110
申请日:2019-01-31
Applicant: Texas Instruments Incorporated
Inventor: Woochan Kim , Benjamin Allen Samples , Vivek Kishorechand Arora
IPC: H01L23/52 , H01L23/522 , H01L23/538 , H01L23/532 , H01L25/07 , H01L49/02 , H01L23/00 , H01L25/00
Abstract: A packaged electronic device includes a semiconductor die with an electronic component and a contact structure connected to the electronic component, as well as an organic panel frame, a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame, and a ceramic substrate mounted to a first side of the semiconductor die.
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