公开(公告)号：US20240339421A1

公开(公告)日：2024-10-10

申请号：US18748127

申请日：2024-06-20

Applicant: ROHM CO., LTD.

Inventor： Masatoshi AKETA

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/3672 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/32 ,  H01L25/18 ,  H01L21/561 ,  H01L24/11 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/1162 ,  H01L2224/1184 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer.

公开(公告)号：US20240290676A1

公开(公告)日：2024-08-29

申请号：US18174039

申请日：2023-02-24

Applicant: Texas Instruments Incorporated

Inventor： Masamitsu Matsuura ,  Makoto Shibuya ,  Daiki Komatsu ,  Kengo Aoya

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/367 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49811 ,  H01L25/16 ,  H01L23/49589 ,  H01L23/49833 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/2919 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/40137 ,  H01L2224/40475 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48175 ,  H01L2224/48229 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13091

Abstract: A microelectronic device includes one or more electronic components attached to a package substrate which has an exposed surface to provide an area for mounting a heatsink. The microelectronic device includes one or more leads that are electrically connected to the electronic component. The lead extends away from the exposed surface of the package substrate. The microelectronic device includes a shielding dielectric material that laterally surrounds the lead and extends over the lead between the lead and the exposed surface of the package substrate. An electronic system includes the microelectronic device and a circuit board electrically connected to the lead. The electronic system also includes a heatsink attached to the exposed surface of the package substrate.

公开(公告)号：US20240266241A1

公开(公告)日：2024-08-08

申请号：US18398896

申请日：2023-12-28

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Sota YAMAGUCHI

IPC: H01L23/367

CPC classification number: H01L23/367 ,  H01L24/32 ,  H01L25/072 ,  H01L2224/32225 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes a substrate, a semiconductor element on the substrate, and a cooler that cools the substrate, wherein the cooler includes a cooling body having a first part, and a second part protruding from the first part toward the substrate, and a cooling fin fixed within the second part, the cooling fin being exposed to an exterior of the device on a side thereof facing away from the substrate.

公开(公告)号：US20240203841A1

公开(公告)日：2024-06-20

申请号：US17798055

申请日：2022-05-27

Applicant: STARPOWER SEMICONDUCTOR LTD.

Inventor： Danting FENG ,  Junjun FANG

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L25/07

CPC classification number: H01L23/49555 ,  H01L24/45 ,  H01L24/48 ,  H01L25/072 ,  H01L23/49811 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: The invention discloses a novel packaging structure of a power semiconductor module, which mainly comprises an insulating radiating fin, a metal lead frame unit and a chip unit. The insulating radiating fin comprises an insulating layer, and an inner metal conducting layer and an outer metal conducting layer which are respectively arranged on two sides of the insulating layer; the metal lead frame unit mainly comprises a frame pin input portion, a frame pin output portion and a frame pin signal portion, the frame pin input portion is arranged on an upper side of the inner metal conducting layer in a solder welding mode, and the chip unit is welded to the middle of the inner metal conductive layer. The frame pin output portion is provided with an inner concave portion.

公开(公告)号：US11996354B2

公开(公告)日：2024-05-28

申请号：US18298160

申请日：2023-04-10

Applicant: Rohm Co., Ltd.

Inventor： Koshun Saito ,  Hiroyuki Sakairi ,  Yasufumi Matsuoka ,  Kenichi Yoshimochi

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/48 ,  H01L2224/48245 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1067 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/30101 ,  H01L2924/30107

Abstract: A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

公开(公告)号：US11990455B2

公开(公告)日：2024-05-21

申请号：US17596060

申请日：2020-06-19

Applicant: ROHM CO., LTD.

Inventor： Hiroyuki Sakairi ,  Yusuke Nakakohara ,  Ken Nakahara

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/495 ,  H02M1/08 ,  H02M3/00

CPC classification number: H01L25/16 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/06 ,  H01L24/38 ,  H01L24/41 ,  H01L24/49 ,  H01L24/73 ,  H02M1/08 ,  H02M3/003 ,  H01L24/40 ,  H01L24/48 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0615 ,  H01L2224/38 ,  H01L2224/4009 ,  H01L2224/40106 ,  H01L2224/40245 ,  H01L2224/41175 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/4903 ,  H01L2224/49112 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1067 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091

Abstract: A semiconductor device includes a conductive member including first, second and third conductors mutually spaced, a first semiconductor element having a first obverse surface provided with a first drain electrode, a first source electrode and a first gate electrode, and a second semiconductor element having a second obverse surface provided with a second drain electrode, a second source electrode and a second gate electrode. The first conductor is electrically connected to the first source electrode and the second drain electrode. The second conductor is electrically connected to the second source electrode. As viewed in a first direction crossing the first obverse surface, the second conductor is adjacent to the first conductor in a second direction crossing the first direction. The third conductor is electrically connected to the first drain electrode and is adjacent to the first conductor and the second conductor as viewed in the first direction.

公开(公告)号：US20240145414A1

公开(公告)日：2024-05-02

申请号：US18483159

申请日：2023-10-09

Applicant: Wolfspeed, Inc.

Inventor： Gerard Bouisse

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H03F1/56 ,  H03F3/195

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/16 ,  H03F1/565 ,  H03F3/195 ,  H01L2223/6655 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/14152 ,  H01L2224/16235 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F2200/222

Abstract: A radio frequency transistor amplifier package includes a package substrate with input, output, and ground terminals, and a transistor die on the package substrate. The transistor die includes a semiconductor structure having a plurality of transistors and gate, drain, and source contacts electrically coupled thereto. An inductance adjustment element is electrically coupled between the source contacts and the ground terminal, and is configured to provide a stability factor K of greater than or equal to 1 for a first operating frequency range of the transistor die. Related devices and methods are also discussed.

公开(公告)号：US20240145349A1

公开(公告)日：2024-05-02

申请号：US18474325

申请日：2023-09-26

Applicant: DENSO CORPORATION

Inventor： TAKAHIRO HIRANO ,  MASAYOSHI NISHIHATA ,  CHIHIRO KATO

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/49517 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L25/072 ,  H01L23/49562 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/37644 ,  H01L2224/37655 ,  H01L2224/40137 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1067 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes: a first element for one of upper and lower arm circuits; a second element for the other of the upper and lower arm circuits; a first wiring having a first mounting portion on which the first element is disposed and a first power supply terminal portion connected with the first mounting portion; a second wiring having a second mounting portion on which the second element is disposed and an output terminal portion connected with the second mounting portion; a clip configured to electrically connect a main electrode of the first element and the second mounting portion; and a third wiring having a connection portion to which a main electrode of the second element is connected and a second power supply terminal portion connected with the connection portion. The third wiring is extended parallel to the first wiring and the clip.

公开(公告)号：US11955398B2

公开(公告)日：2024-04-09

申请号：US17354110

申请日：2021-06-22

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Eri Ogawa

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/66 ,  H01L23/00 ,  H01L23/043 ,  H01L23/34 ,  H01L23/373 ,  H01L25/07

CPC classification number: H01L23/34 ,  H01L21/4817 ,  H01L21/4871 ,  H01L22/12 ,  H01L23/043 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/32225 ,  H01L2224/40225 ,  H01L2224/73263 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1067 ,  H01L2924/12036 ,  H01L2924/1302 ,  H01L2924/13032 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/1715

Abstract: A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.

公开(公告)号：US11881476B2

公开(公告)日：2024-01-23

申请号：US17664841

申请日：2022-05-24

Applicant: Semtech Corporation

Inventor： Changjun Huang ,  Jonathan Clark

IPC: H01L25/00 ,  H01L23/60 ,  H01L23/495 ,  H01L27/02 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/49575 ,  H01L23/60 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L21/304 ,  H01L21/561 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/85 ,  H01L27/0255 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08148 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/8082 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/8182 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1033 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/1203 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/11901 ,  H01L2224/11849 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/80 ,  H01L2224/97 ,  H01L2224/80 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45139 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.