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    Gate-All-Around Structure with Self Substrate Isolation and Methods of Forming the Same
    21.
    发明申请
    Gate-All-Around Structure with Self Substrate Isolation and Methods of Forming the Same 有权

    公开(公告)号：US20220029028A1

    公开(公告)日：2022-01-27

    申请号：US17498093

    申请日：2021-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

    PMOSFET Source Drain
    22.
    发明申请
    PMOSFET Source Drain 有权

    公开(公告)号：US20210328020A1

    公开(公告)日：2021-10-21

    申请号：US17021765

    申请日：2020-09-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Kuan-Lun Cheng

    IPC: H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

    Abstract: A semiconductor device according to the present disclosure includes a first source/drain epitaxial feature and a second source/drain epitaxial feature each having an outer liner layer and an inner filler layer, a plurality of channel members extending between the first source/drain epitaxial feature and the second source/drain epitaxial feature along a first direction, and a gate structure disposed over and around the plurality of channel members. The plurality of channel members are in contact with the outer liner layer and are spaced apart from the inner filler layer. The outer liner layer comprises germanium and boron and the inner filler layer comprises germanium and gallium.

    Gate-all-around structure with self substrate isolation and methods of forming the same
    23.
    发明授权
    Gate-all-around structure with self substrate isolation and methods of forming the same 有权

    公开(公告)号：US11145765B2

    公开(公告)日：2021-10-12

    申请号：US16583449

    申请日：2019-09-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

    Semiconductor devices
    24.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11088256B2

    公开(公告)日：2021-08-10

    申请号：US16667947

    申请日：2019-10-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

    Semiconductor devices
    25.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11088255B2

    公开(公告)日：2021-08-10

    申请号：US16415193

    申请日：2019-05-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.

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