公开(公告)号：US20220359310A1

公开(公告)日：2022-11-10

申请号：US17815068

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang Shih ,  Pang-Yen Tsai

IPC: H01L21/8238 ,  H01L29/45 ,  C30B29/52 ,  C30B29/08 ,  C30B33/12 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/24 ,  C30B25/02

Abstract: A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

公开(公告)号：US11264485B2

公开(公告)日：2022-03-01

申请号：US16662333

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Han Wang ,  Ding-Kang Shih ,  Chun-Hsiung Lin ,  Teng-Chun Tsai ,  Zhi-Chang Lin ,  Akira Mineji ,  Yao-Sheng Huang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

公开(公告)号：US11233134B2

公开(公告)日：2022-01-25

申请号：US16721352

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Wei Chu ,  Ding-Kang Shih ,  Sung-Li Wang ,  Yasutoshi Okuno

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08

Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

公开(公告)号：US11133223B2

公开(公告)日：2021-09-28

申请号：US16512722

申请日：2019-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang Shih ,  Cheng-Long Chen ,  Pang-Yen Tsai

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311

Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes providing a workpiece comprising a first source/drain region in a first device region and a second source/drain region in a second device region, depositing a dielectric layer over the first source/drain region and the second source drain region, forming a first via opening in the dielectric layer to expose the first source/drain region and a second via opening in the dielectric layer to expose the second source/drain region, annealing the workpiece to form a first semiconductor oxide feature over the exposed first source/drain region and a second semiconductor oxide feature over the exposed second source/drain region, removing the first semiconductor oxide feature to expose the first source/drain region in the first via opening in dielectric layer, and selectively forming a first epitaxial feature over the exposed first source/drain region.

公开(公告)号：US20210126106A1

公开(公告)日：2021-04-29

申请号：US16662333

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Han WANG ,  Ding-Kang Shih ,  Chun-Hsiung Lin ,  Teng-Chun Tsai ,  Zhi-Chang Lin ,  Akira Mineji ,  Yao-Sheng Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

公开(公告)号：US10937876B2

公开(公告)日：2021-03-02

申请号：US16276833

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang Shih ,  Sung-Li Wang ,  Pang-Yen Tsai

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165

Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

公开(公告)号：US20210020522A1

公开(公告)日：2021-01-21

申请号：US16512722

申请日：2019-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ding-Kang Shih ,  Cheng-Long Chen ,  Pang-Yen Tsai

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311

Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes providing a workpiece comprising a first source/drain region in a first device region and a second source/drain region in a second device region, depositing a dielectric layer over the first source/drain region and the second source drain region, forming a first via opening in the dielectric layer to expose the first source/drain region and a second via opening in the dielectric layer to expose the second source/drain region, annealing the workpiece to form a first semiconductor oxide feature over the exposed first source/drain region and a second semiconductor oxide feature over the exposed second source/drain region, removing the first semiconductor oxide feature to expose the first source/drain region in the first via opening in dielectric layer, and selectively forming a first epitaxial feature over the exposed first source/drain region.