公开(公告)号：US20220013412A1

公开(公告)日：2022-01-13

申请号：US16925918

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Wei Chen ,  Jian-Jou Lian ,  Tzu-Ang Chiang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L21/8234 ,  H01L21/027 ,  G03F7/09 ,  H01L29/66 ,  G03F1/46

Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.

公开(公告)号：US10699944B2

公开(公告)日：2020-06-30

申请号：US16145457

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/48 ,  H01L21/306

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US10676668B2

公开(公告)日：2020-06-09

申请号：US16220507

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Neng-Jye Yang ,  Kuo Bin Huang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Yu-Wen Wang ,  Jian-Jou Lian ,  Shih Min Chang

IPC: C09K13/02 ,  H01L29/66 ,  H01L21/3213 ,  C09K13/08 ,  C09K13/00

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.

公开(公告)号：US10179878B2

公开(公告)日：2019-01-15

申请号：US15657537

申请日：2017-07-24

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Neng-Jye Yang ,  Kuo Bin Huang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Yu-Wen Wang ,  Jian-Jou Lian ,  Shih Min Chang

IPC: H01L21/3213 ,  H01L29/66 ,  C09K13/08 ,  C09K13/02

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.