公开(公告)号：US11855193B2

公开(公告)日：2023-12-26

申请号：US17648166

申请日：2022-01-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jian-Jou Lian ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Chieh-Wei Chen ,  Tzu-Ang Chiang

IPC分类号： H01L29/66 ,  H01L21/84 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/845 ,  H01L29/7854

摘要： A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

公开(公告)号：US11854903B2

公开(公告)日：2023-12-26

申请号：US17073784

申请日：2020-10-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chi Huang ,  Kuo-Bin Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/311

CPC分类号： H01L21/823481 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L21/31133 ,  H01L27/0924

摘要： A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

公开(公告)号：US20220328683A1

公开(公告)日：2022-10-13

申请号：US17852755

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

摘要： A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US11424347B2

公开(公告)日：2022-08-23

申请号：US16899119

申请日：2020-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ssu-Yu Liao ,  Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

摘要： Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

公开(公告)号：US20220173226A1

公开(公告)日：2022-06-02

申请号：US17676335

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234

摘要： Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US11114436B2

公开(公告)日：2021-09-07

申请号：US16947758

申请日：2020-08-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L27/088 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

摘要： Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US20210057287A1

公开(公告)日：2021-02-25

申请号：US17073784

申请日：2020-10-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chi Huang ,  Kuo-Bin Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78

摘要： A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

公开(公告)号：US20200350418A1

公开(公告)日：2020-11-05

申请号：US16928423

申请日：2020-07-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/49 ,  H01L29/08

摘要： Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.

公开(公告)号：US10748898B2

公开(公告)日：2020-08-18

申请号：US16404101

申请日：2019-05-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

摘要： Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US10658221B2

公开(公告)日：2020-05-19

申请号：US15812112

申请日：2017-11-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wang-Hua Lin ,  Chun-Liang Tai ,  Chun-Hsiang Fan ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC分类号： H01L21/687 ,  H01L21/67 ,  B08B3/08 ,  B08B3/10

摘要： A method for cleaning a semiconductor wafer is provided. The method includes placing a semiconductor wafer over a supporter arranged around a central axis of a spin base. The method further includes securing the semiconductor wafer using a clamping member positioned on the supporter. The movement of the semiconductor wafer during the placement of the semiconductor wafer over the supporter is guided by a guiding member located over the clamping member. The method also includes spinning the semiconductor wafer by rotating the spin base about the central axis. In addition, the method includes dispensing a processing liquid over the semiconductor wafer.