公开(公告)号：US11923437B2

公开(公告)日：2024-03-05

申请号：US17452178

申请日：2021-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/12 ,  H01L29/66545

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

公开(公告)号：US11735426B2

公开(公告)日：2023-08-22

申请号：US17401845

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Li-Min Chen ,  Neng-Jye Yang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L21/28247 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/32134 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

公开(公告)号：US20210384034A1

公开(公告)日：2021-12-09

申请号：US17401845

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Li-Min Chen ,  Neng-Jye Yang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

公开(公告)号：US11195752B1

公开(公告)日：2021-12-07

申请号：US16887316

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu Shih Wang ,  Kuo-Bin Huang ,  Ming-Hsi Yeh ,  Po-Nan Yeh

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/3213 ,  H01L23/535 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49

Abstract: A method for forming a semiconductor device includes forming a metal contact on a substrate, forming a first dielectric on the metal contact, forming a first opening in the first dielectric, and performing a wet etch on a bottom surface of the first opening through a first etch stop layer (ESL) over the metal contact. The wet etch forms a first recess in a top surface of the metal contact. An upper width of the first recess is smaller than a lower width of the first recess. A first conductive feature is formed in the first recess and the first opening.

公开(公告)号：US20210202238A1

公开(公告)日：2021-07-01

申请号：US16907634

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/027 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L29/78

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US20210134660A1

公开(公告)日：2021-05-06

申请号：US16906615

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US10283417B1

公开(公告)日：2019-05-07

申请号：US15833721

申请日：2017-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further includes a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer includes metal phosphate and the second self-protective layer includes boron including complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.

公开(公告)号：US20240371688A1

公开(公告)日：2024-11-07

申请号：US18775995

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20240194522A1

公开(公告)日：2024-06-13

申请号：US18586925

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/30604 ,  H01L21/4857 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US11854903B2

公开(公告)日：2023-12-26

申请号：US17073784

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Kuo-Bin Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/823481 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L21/31133 ,  H01L27/0924

Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.