公开(公告)号：US20230343699A1

公开(公告)日：2023-10-26

申请号：US17890194

申请日：2022-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsuan LU ,  Lin-Yu HUANG ,  Li-Zhen YU ,  Sheng-Tsung WANG ,  Chung-Liang CHENG ,  Huan-Chieh SU ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41775 ,  H01L29/41733 ,  H01L23/5283

Abstract: A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.

公开(公告)号：US20230137307A1

公开(公告)日：2023-05-04

申请号：US17693203

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Li-Zhen YU ,  Huan-Chieh SU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The integrated circuit includes a backside trench through the substrate that removes a lowest semiconductor nanosheet of the first nanosheet transistor while leaving the lowest semiconductor nanosheet of the second nanosheet transistor. The backside trench is filled with a dielectric material.

公开(公告)号：US20220037191A1

公开(公告)日：2022-02-03

申请号：US16944018

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

公开(公告)号：US20220028780A1

公开(公告)日：2022-01-27

申请号：US16935135

申请日：2020-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

公开(公告)号：US20210376092A1

公开(公告)日：2021-12-02

申请号：US17401970

申请日：2021-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L27/088 ,  H01L27/092

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US20210134669A1

公开(公告)日：2021-05-06

申请号：US16939994

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/522

Abstract: The present disclosure describes a method for forming an interconnect structure. The method can include forming a first layer of insulating material on a substrate, forming a via recess within the layer of insulating material, filling the via recess with a layer of conductive material, selectively growing a second layer of insulating material over the first layer of insulating material, and opening the second layer of insulating material to the layer of conductive material while growing the second layer of insulating material.

公开(公告)号：US20210126129A1

公开(公告)日：2021-04-29

申请号：US16808770

申请日：2020-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a cap layer formed over the gate structure. The structure also includes a contact structure formed over the gate structure penetrating through the cap layer. The structure also includes an isolation film formed over sidewalls of the contact structure. The isolation film is separated from the gate structure, and a bottom surface of the isolation film is below a top surface of the cap layer.

公开(公告)号：US20210098368A1

公开(公告)日：2021-04-01

申请号：US16855690

申请日：2020-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a first metal via passing through the first insulating layer, and a second insulating layer formed over the first insulating layer. The semiconductor device structure also includes a first metal hump surrounded by the second insulating layer and connected to the top surface of the first metal via. The first metal hump covers the portion of the first insulating layer adjacent to the first metal via. In addition, the semiconductor device structure includes a metal line formed in the second insulating layer and electrically connected to the first metal via, and a conductive liner covering the first metal hump and separating the metal line from the second insulating layer and the first metal hump.

公开(公告)号：US20210057530A1

公开(公告)日：2021-02-25

申请号：US16546799

申请日：2019-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285

Abstract: A semiconductor device includes a substrate, a source/drain structure, a source/drain contact, a gate structure, a first etching stop layer, and a via contact. The source/drain structure is over the substrate. The source/drain contact is over the source/drain contact. The gate structure is over the substrate. The first etching stop layer is over the gate structure, in which the first etching stop layer includes a first portion and a second portion, and a thickness of the first portion is lower than a thickness the second portion. The via contact extends along a top surface of the first portion of the first etching stop layer to a sidewall of the second portion of the first etching stop layer.