公开(公告)号：US20250029925A1

公开(公告)日：2025-01-23

申请号：US18787880

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

公开(公告)号：US20240096701A1

公开(公告)日：2024-03-21

申请号：US18172240

申请日：2023-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Ching-Wei TSAI ,  Shang-Wen CHANG ,  Yi-Hsun CHIU ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

公开(公告)号：US20220352074A1

公开(公告)日：2022-11-03

申请号：US17476962

申请日：2021-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

公开(公告)号：US20210407994A1

公开(公告)日：2021-12-30

申请号：US16915930

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh SU ,  Chun-Yuan CHEN ,  Pei-Yu WANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source region, a drain region, and a gate electrode layer disposed between the source region and the drain region. The gate electrode layer includes a first surface facing the source region, and the first surface includes an edge portion having a first height. The gate electrode layer further includes a second surface opposite the first surface and facing the drain region. The second surface includes an edge portion having a second height. The second height is different from the first height.

公开(公告)号：US20230343699A1

公开(公告)日：2023-10-26

申请号：US17890194

申请日：2022-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsuan LU ,  Lin-Yu HUANG ,  Li-Zhen YU ,  Sheng-Tsung WANG ,  Chung-Liang CHENG ,  Huan-Chieh SU ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41775 ,  H01L29/41733 ,  H01L23/5283

Abstract: A device includes a substrate, a vertical stack of nanostructure channels over the substrate, a gate structure wrapping around the nanostructure channels, and a source/drain region on the substrate. The device further includes a source/drain contact in contact with the source/drain region. The source/drain contact includes a core layer of a first material. A source/drain via is over and in contact with the source/drain contact. The source/drain via is the first material. A gate via is over and in electrical connection with the gate structure. The gate via is the first material.

公开(公告)号：US20230335444A1

公开(公告)日：2023-10-19

申请号：US17941708

申请日：2022-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Tsung WANG ,  Huan-Chieh SU ,  Chun-Yuan CHEN ,  Lin-Yu HUANG ,  Ching-Wei TSAI ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L27/12

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. The first and second nanostructure each include gate electrodes. A backside trench separates the first gate electrode from the second gate electrode. A bulk dielectric material fills the backside trench. A gate cap metal electrically connects the first gate electrode to the second gate electrode.

公开(公告)号：US20230137307A1

公开(公告)日：2023-05-04

申请号：US17693203

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Li-Zhen YU ,  Huan-Chieh SU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The integrated circuit includes a backside trench through the substrate that removes a lowest semiconductor nanosheet of the first nanosheet transistor while leaving the lowest semiconductor nanosheet of the second nanosheet transistor. The backside trench is filled with a dielectric material.

公开(公告)号：US20210272856A1

公开(公告)日：2021-09-02

申请号：US16947398

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting PAN ,  Huan-Chieh SU ,  Zhi-Chang LIN ,  Shi Ning JU ,  Yi-Ruei JHAN ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US20240112959A1

公开(公告)日：2024-04-04

申请号：US18526839

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting PAN ,  Zhi-Chang LIN ,  Yi-Ruei JHAN ,  Chi-Hao WANG ,  Huan-Chieh SU ,  Shi Ning JU ,  Kuo-Cheng CHIANG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823878 ,  H01L21/02603 ,  H01L21/31111 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

公开(公告)号：US20230343854A1

公开(公告)日：2023-10-26

申请号：US17879529

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh SU ,  Lin-Yu Huang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468

Abstract: A semiconductor device with air spacer structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, nanostructured channel regions disposed on the substrate, a gate structure surrounding the nanostructured channel regions, a first air spacer disposed on the gate structure, a source/drain (S/D) region disposed on the substrate, and a contact structure disposed on the S/D region. The contact structure includes a silicide layer disposed on the S/D region, a conductive layer disposed on the silicide layer, a dielectric layer disposed along a sidewall of the conductive layer, and a second air spacer disposed along a sidewall of the dielectric layer.