公开(公告)号：US20250142926A1

公开(公告)日：2025-05-01

申请号：US19009482

申请日：2025-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H10D64/23 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83 ,  H10D84/85

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US20230326986A1

公开(公告)日：2023-10-12

申请号：US18335741

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/41775 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/6653 ,  H01L21/28114 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/517

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

公开(公告)号：US20220157949A1

公开(公告)日：2022-05-19

申请号：US17649312

申请日：2022-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

公开(公告)号：US20230335645A1

公开(公告)日：2023-10-19

申请号：US17884394

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Sheng-Tsung WANG ,  Chun-Yuan CHEN ,  Li-Zhen YU ,  Lin-Yu HUANG ,  Huan-Chieh SU

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/41 ,  H01L29/417

CPC classification number: H01L29/78609 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775

Abstract: A device includes a gate electrode and a gate dielectric surrounding the gate electrode. The gate electrode surrounds a nanostructure. The nanostructure includes stacked nanosheets. The gate dielectric is formed by a high-k (HK) material. The HK material covers sidewalls of the gate electrode in a direction aligned to adjacent devices. Portions of the HK material are recessed from the sidewalls and refilled by a dielectric material with a dielectric constant less than the HK material and an electrical isolation capability greater than the HK material. Replacing the HK material over the sidewalls of the gate electrode with the dielectric material enhances electrical isolation between the gate electrode with adjacent contacts. Consequently, it can reduce electrical leakage between metal gate (MG) contacts and metal-to-device (MD) contacts in scaled transistors of an integrated circuit (IC).

公开(公告)号：US20220115510A1

公开(公告)日：2022-04-14

申请号：US17069344

申请日：2020-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Lin-Yu Huang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

公开(公告)号：US20220093448A1

公开(公告)日：2022-03-24

申请号：US17199085

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Huan-Chieh SU ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: An integrated circuit (IC) structure includes a transistor, a front-side interconnection structure, a backside via, and a backside interconnection structure. The transistor includes a source/drain epitaxial structure. The front-side interconnection structure is on a front-side of the transistor. The backside via is connected to the source/drain epitaxial structure of the transistor. The backside interconnection structure is connected to the backside via and includes a conductive feature, a dielectric layer, and a spacer structure. The conductive feature is connected to the backside via. The dielectric layer laterally surrounds the conductive feature. The spacer structure is between the conductive feature and the dielectric layer and has an air gap.

公开(公告)号：US20240395608A1

公开(公告)日：2024-11-28

申请号：US18791303

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao CHANG ,  Jia-Chuan YOU ,  Li-Zhen YU ,  Lin-Yu HUANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.

公开(公告)号：US20210336012A1

公开(公告)日：2021-10-28

申请号：US16948712

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

公开(公告)号：US20210305382A1

公开(公告)日：2021-09-30

申请号：US16948745

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

公开(公告)号：US20200243519A1

公开(公告)日：2020-07-30

申请号：US16257375

申请日：2019-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Tien-Lu LIN ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/033 ,  H01L21/8234

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The method includes forming a dielectric layer over the first epitaxial structure, the second epitaxial structure, and the semiconductor substrate. The method includes forming a first mask layer over the dielectric layer and between the first epitaxial structure and the second epitaxial structure. The method includes forming a second mask layer over the dielectric layer and the first mask layer. The method includes partially removing the dielectric layer covering the first epitaxial structure and the second epitaxial structure. The method includes removing the first mask layer. The method includes forming a first conductive layer and a second conductive layer respectively in the first recess and the second recess.