公开(公告)号：US20150067616A1

公开(公告)日：2015-03-05

申请号：US14011790

申请日：2013-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung HSU ,  Yuan-Te HOU ,  Li-Chun TIEN ,  Hui-Zhong ZHUANG ,  Fang-Yu FAN ,  Wen-Hao CHEN ,  Ting Yu CHEN

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Abstract translation: 一种方法包括将一个或多个单元与选择指南进行比较，并将满足选择准则的单元存储在非瞬态计算机可读存储介质中，以基于该比较创建单元库。 选择指南确定单元格内边界引脚的合适位置。

公开(公告)号：US20140013292A1

公开(公告)日：2014-01-09

申请号：US13723248

申请日：2012-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao CHEN ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/84

Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.