公开(公告)号：US20240387504A1

公开(公告)日：2024-11-21

申请号：US18785842

申请日：2024-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

Abstract: An integrated circuit (IC) device includes first to fourth circuits configured to perform corresponding functions. The first to fourth circuits correspondingly include first to fourth active regions extending along a first direction, and further include a plurality of gate regions extending along a second direction transverse to the first direction. Adjacent gate regions among the plurality of gate regions are spaced from each other along the first direction by one gate region pitch. The first active region and the second active region correspondingly have a first source/drain region and a second source/drain region spaced from each other, along the first direction, by one gate region pitch. The first source/drain region is a drain region. The plurality of gate regions includes a dummy gate region between the first source/drain region and the second source/drain region. The third active region and the fourth active region share a common source region.

公开(公告)号：US20150249080A1

公开(公告)日：2015-09-03

申请号：US14714369

申请日：2015-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Yu MA ,  Bo-Ting CHEN ,  Ting Yu CHEN ,  Kuo-Ji CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L27/06 ,  H01L27/118

CPC classification number: H01L27/0288 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/11807 ,  H01L28/20 ,  H01L28/24

Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

Abstract translation: 集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。 在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。 制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及 施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

公开(公告)号：US20210407985A1

公开(公告)日：2021-12-30

申请号：US16910658

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/392

Abstract: A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region.

公开(公告)号：US20230197723A1

公开(公告)日：2023-06-22

申请号：US18168065

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali KESHAVARZI ,  Ta-Pen GUO ,  Shu-Hui SUNG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Ting Yu CHEN ,  Min CAO ,  Yung-Chin HOU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/0649 ,  H01L29/495 ,  H01L2924/0002

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US20230154917A1

公开(公告)日：2023-05-18

申请号：US18156605

申请日：2023-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L27/092

Abstract: A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.

公开(公告)号：US20150067616A1

公开(公告)日：2015-03-05

申请号：US14011790

申请日：2013-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung HSU ,  Yuan-Te HOU ,  Li-Chun TIEN ,  Hui-Zhong ZHUANG ,  Fang-Yu FAN ,  Wen-Hao CHEN ,  Ting Yu CHEN

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Abstract translation: 一种方法包括将一个或多个单元与选择指南进行比较，并将满足选择准则的单元存储在非瞬态计算机可读存储介质中，以基于该比较创建单元库。 选择指南确定单元格内边界引脚的合适位置。