公开(公告)号：US06486708B2

公开(公告)日：2002-11-26

申请号：US10122385

申请日：2002-04-16

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

IPC分类号： H03K19094

CPC分类号： G06F17/505 ,  H03K19/1737

摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

公开(公告)号：US06433588B1

公开(公告)日：2002-08-13

申请号：US09940597

申请日：2001-08-29

申请人： Shunzo Yamashita ,  Kazuo Yano

发明人： Shunzo Yamashita ,  Kazuo Yano

IPC分类号： H03K19094

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 转换为2输入，1输出，1路控制输入通道晶体管选择器，合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值，逻辑上等效于通过晶体管选择器的NAND或NOR逻辑（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通道小 晶体管逻辑电路）。

公开(公告)号：US06323690B1

公开(公告)日：2001-11-27

申请号：US09610697

申请日：2000-07-05

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

IPC分类号： H03K19094

CPC分类号： G06F17/505 ,  H03K19/1737

摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

公开(公告)号：US06260185B1

公开(公告)日：2001-07-10

申请号：US08930219

申请日：1997-10-20

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06G748

CPC分类号： G06F17/505 ,  H03K19/1736 ,  H03K19/1737

摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

公开(公告)号：US07986243B2

公开(公告)日：2011-07-26

申请号：US12633284

申请日：2009-12-08

申请人： Yoshihiro Wakisaka ,  Shunzo Yamashita ,  Toshiyuki Odaka ,  Norio Ohkubo

发明人： Yoshihiro Wakisaka ,  Shunzo Yamashita ,  Toshiyuki Odaka ,  Norio Ohkubo

IPC分类号： G08B21/00

CPC分类号： G01D3/08 ,  Y10T307/74

摘要： A network system including: a first sensor device which includes a first sensor unit which detects an action of a detection object; and a first transmission unit which transmits first data regarding the action and first identification information to a server via a first base station: a second sensor device which includes; a second sensor unit which obtains sensing data; and a second transmission unit which transmits second data including the sensing data and second identification information to the server via a second base station; wherein the server is configured to: associate the first and second data based on the detection of the action; to access predetermined normal data correlating data; and, detect an abnormal condition if a combination of the action detected via the first sensor unit and the sensing data obtained by the second sensor unit conflict with the correlated normal data.

摘要翻译： 一种网络系统，包括：第一传感器装置，其包括检测检测对象的动作的第一传感器单元; 以及第一传输单元，其经由第一基站向服务器发送关于所述动作的第一数据和所述第一识别信息;第二传感器装置， 获取感测数据的第二传感器单元; 以及第二传输单元，其经由第二基站向服务器发送包括感测数据和第二识别信息的第二数据; 其中所述服务器被配置为：基于所述动作的检测来关联所述第一和第二数据; 访问预定的正常数据相关数据; 并且如果通过第一传感器单元检测到的动作和由第二传感器单元获得的感测数据的组合与相关联的正常数据冲突，则检测异常状况。

公开(公告)号：US07593752B2

公开(公告)日：2009-09-22

申请号：US11723691

申请日：2007-03-21

申请人： Koji Ara ,  Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura

发明人： Koji Ara ,  Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura

IPC分类号： H04M1/00

CPC分类号： G01D5/00 ,  G01D21/00 ,  H04W28/06 ,  H04W28/14 ,  H04W52/0216 ,  H04W52/0219 ,  H04W84/18

摘要： This invention achieves lower electric power consumption of a sensor node for carrying out an intermittent operation, in a sensor net system. A time when the sensor node transmits a signal to a base station is estimated. Then, in accordance with the estimation, a table for storing a signal transmitted from the sensor node is installed in a wireless section of the base station. Consequently, a communication time between the sensor node and the base station can be made shorter. Also, a start time of a micro computer is set for RTC inside the sensor node, so the micro computer inside the sensor node can be put in the standby state.

公开(公告)号：US07512418B2

公开(公告)日：2009-03-31

申请号：US11208658

申请日：2005-08-23

申请人： Koji Ara ,  Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura

发明人： Koji Ara ,  Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura

IPC分类号： H04M1/00

CPC分类号： G01D5/00 ,  G01D21/00 ,  H04W28/06 ,  H04W28/14 ,  H04W52/0216 ,  H04W52/0219 ,  H04W84/18

摘要： This invention achieves lower electric power consumption of a sensor node for carrying out an intermittent operation, in a sensor net system. A time when the sensor node transmits a signal to a base station is estimated. Then, in accordance with the estimation, a table for storing a signal transmitted from the sensor node is installed in a wireless section of the base station. Consequently, a communication time between the sensor node and the base station can be made shorter. Also, a start time of a micro computer is set for RTC inside the sensor node, so the micro computer inside the sensor node can be put in the standby state.

摘要翻译： 本发明在传感器网络系统中实现用于进行间歇操作的传感器节点的较低的电力消耗。 估计传感器节点向基站发送信号的时间。 然后，根据该估计，将用于存储从传感器节点发送的信号的表安装在基站的无线部分中。 因此，可以使传感器节点与基站之间的通信时间更短。 此外，传感器节点内的RTC设置微计算机的开始时间，因此传感器节点内的微计算机可以处于待机状态。

公开(公告)号：US20080130253A1

公开(公告)日：2008-06-05

申请号：US11976041

申请日：2007-10-19

申请人： Shunzo Yamashita

发明人： Shunzo Yamashita

IPC分类号： H05K7/00

CPC分类号： H05K1/181 ,  H05K1/0218 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/10151 ,  H05K2201/10689 ,  H05K2203/1572 ,  Y02P70/611

摘要： An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

摘要翻译： 优选作为传感器节点的电子电路具有高灵敏度的无线电功能，并且能够执行低功耗操作。 电子设备有一个板子; 用于连接传感器的连接器; 第一信号处理器电路，通过连接器从传感器接收传感器数据的输入并形成传输数据; 以及将来自第一信号处理器电路的传输信号转换成高频信号的第二信号处理器电路。 连接器和第一信号处理器电路安装在板的第一表面上，并且第二信号处理器电路安装在板的第二表面上。

公开(公告)号：US20080068194A1

公开(公告)日：2008-03-20

申请号：US11870760

申请日：2007-10-11

申请人： Yoshihiro WAKISAKA ,  Shunzo Yamashita ,  Toshiyuki Odaka ,  Norio Ohkubo

发明人： Yoshihiro WAKISAKA ,  Shunzo Yamashita ,  Toshiyuki Odaka ,  Norio Ohkubo

IPC分类号： G08B21/00

CPC分类号： G01D3/08 ,  Y10T307/74

摘要： A sensor device wherein when a first sensor detects a detection object, the first sensor changes its output voltage level, and when the processor unit detects the change of the output voltage level of the first sensor as an interrupt signal, the drive voltage level of the first sensor is switched from the first signal level to the second signal level which is different from the first signal level and the drive voltage level of the second sensor is switched from the second signal level to the first signal level which is different from the second signal level.

摘要翻译： 一种传感器装置，其中当第一传感器检测到检测对象时，第一传感器改变其输出电压电平，并且当处理器单元检测到作为中断信号的第一传感器的输出电压电平的变化时，驱动电压电平 第一传感器从第一信号电平切换到与第一信号电平不同的第二信号电平，并且第二传感器的驱动电压电平从第二信号电平切换到与第二信号不同的第一信号电平 水平。

公开(公告)号：US20060172784A1

公开(公告)日：2006-08-03

申请号：US11208658

申请日：2005-08-23

申请人： Koji Ara ,  Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura

发明人： Koji Ara ,  Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura

IPC分类号： H04B1/38

CPC分类号： G01D5/00 ,  G01D21/00 ,  H04W28/06 ,  H04W28/14 ,  H04W52/0216 ,  H04W52/0219 ,  H04W84/18

摘要： This invention achieves lower electric power consumption of a sensor node for carrying out an intermittent operation, in a sensor net system. A time when the sensor node transmits a signal to a base station is estimated. Then, in accordance with the estimation, a table for storing a signal transmitted from the sensor node is installed in a wireless section of the base station. Consequently, a communication time between the sensor node and the base station can be made shorter. Also, a start time of a micro computer is set for RTC inside the sensor node, so the micro computer inside the sensor node can be put in the standby state.